High-duty-ratio DDR2 (double data rate) digital delay chain circuit

Abstract

The invention discloses a high-duty-ratio DDR2 digital delay chain circuit. The high-duty-ratio DDR2 digital delay chain circuit comprises a digital delay unit, a write operation clock digital delay chain, and a read-write operation DQS (data strobe signal) digital delay chain, wherein the digital delay unit consists of a clock inverter and a clock selector; and both of the write operation clock digital delay chain and the read-write operation DQS digital delay chain consist of digital delay units in series connection. The high-duty-ratio DDR2 digital delay chain circuit provided by the invention is realized by selecting a full digital circuit so as not to depend on the chip manufacture process, and can realize high-duty-ratio DDR2 write clock and DQS signals, thereby improving the stability and work frequency of DDR2.

Description

Technical field [0001] The invention relates to a high-duty ratio DDR2 digital delay chain circuit, and belongs to the field of high-speed DDR, DDR2, and DDR3 digital circuit design. Background technique [0002] With the continuous development of integrated circuits and the continuous updating of technology, the clock frequency of the chip is continuously improved, and the data throughput of the chip is continuously increased. The duty cycle balance of the synchronous clock signal is very important to ensure the timing performance of the circuit. When it comes to chips, DDR2 needs to have more precise clock accuracy and faster clock frequency. [0003] The traditional digital delay chain circuit generally adopts a digital-analog hybrid design method, which is limited to a specific process, and the design flexibility is not high. Especially in the deep submicron chip process, there is a temperature reversal problem. The traditional digital-analog hybrid delay The impact of the cha...

AI Technical Summary

Problems solved by technology

[0005] Technical problem: the purpose of the invention is to solve the technical problems mentioned in the above-mentioned background, provide a kind of high duty cycle DDR2 digital delay chain circuit, solve existing DDR2 digital delay chain clock duty cycle problem, improve the working frequency of DDR2

[0006] Technical solution: the object of the present invention is to propose a high duty cycle DDR2 digital delay chain circuit for the problem of the clock duty cycle generated by the existing DDR2 digital delay chain circuit and the low application frequency of the existing digital delay chain circuit

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