Low voltage intrinsic NMOS (N-channel metal oxide semiconductor) device and manufacturing method thereof
A manufacturing method and device technology, which are applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of increasing circuit area and decreasing driving current, suppressing source-drain punch-through, reducing circuit area, and facilitating The effect of miniaturization
Active Publication Date: 2013-04-17
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
View PDF5 Cites 2 Cited by
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Although there are not many used in intrinsic NMOS circuits, the decrease in driving current caused by the increase of channel length will eventually lead to the need to connect more devices in parallel in the circuit to meet the performance of the circuit, which indirectly leads to a larger circuit area.
Method used
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View moreImage
Smart Image Click on the blue labels to locate them in the text.
Smart ImageViewing Examples
Examples
Experimental program
Comparison scheme
Effect test
Embodiment Construction
[0036] like figure 1 As shown, the intrinsic NMOS device of the present invention includes: an implanted region 7 is formed on the upper part of the silicon substrate 1, shallow trench isolation 2 is formed on the side of the implanted region 7, an N-type source and drain region 8 is formed on the upper part of the implanted region 7, and implanted A gate oxide layer 3 is formed above the region 7 and the silicon substrate 1, a gate polysilicon layer 4 is formed above the gate oxide layer 3, isolation spacers 6 are formed on both sides of the gate oxide layer 3 and the gate polysilicon layer 4, and N-type source and drain The region 8 and the gate polysilicon layer 4 lead out the connection metal wiring 10 through the contact hole 9, the N-type source and drain region 8 does not overlap with the gate oxide layer 3 and the gate polysilicon layer 4, and the thickness of the gate oxide layer 3 is 2 nanometers to 4 nanometers.
[0037] like figure 2 As shown, the manufacturing ...
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More PUM
Login to View More Abstract
The invention discloses a low voltage intrinsic NMOS (N-channel metal oxide semiconductor) device. The low voltage intrinsic NMOS device is characterized in that an injection region is formed at the upper part of a silicon substrate; a shallow trench isolation is formed beside the injection region; an N-type source and drain region is formed at the upper part of the injection region; a gate oxide layer is formed above the injection region and the silicon substrate; a gate polycrystalline silicon layer is formed above the gate oxide layer; isolation side walls are formed at both sides of the gate oxide layer and the gate polycrystalline silicon layer; and the N-type source and drain region and the gate polycrystalline silicon layer are led out by contact holes to be connected with metal connecting wires. The invention also discloses a manufacturing method of the low voltage intrinsic NMOS device. According to the low voltage intrinsic NMOS device disclosed by the invention, source and drain break-through can be effectively inhibited by improving doping concentrations at both sides of a channel; a manner of lengthening the channel of the device does not need to be adopted to avoid source and drain break-through; and miniaturization of the low voltage intrinsic NMOS device is facilitated and the reduction of the circuit area for applying the low voltage intrinsic NMOS device is facilitated.
Description
technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a low-voltage intrinsic NMOS device. The invention also relates to a method for manufacturing a low-voltage intrinsic NMOS device Background technique [0002] Intrinsic NMOS devices have a low threshold voltage. When its gate voltage is zero volts, it is in an on state. It is often used in analog circuits, mainly as transmission devices. In the SiGe BiCMOS process, in order to isolate external noise and reduce the high-frequency noise of the circuit, especially the low-noise power amplifier (LNA), sometimes it is necessary to use a high-resistivity silicon substrate material, such as a resistivity of 1000ohm.cm substrate. Compared with the conventional silicon substrate with a resistivity of about 10 ohm.cm, the doping concentration of this high-resistivity silicon substrate is reduced by dozens of times. Therefore, for intrinsic NMOS, especially core low-voltage in...
Claims
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More Application Information
Patent Timeline
Login to View More Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L29/08H01L29/10H01L21/336
Inventor 刘冬华石晶钱文生胡君段文婷
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP