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Memory control device and memory control method

A technology of a control device and a control method, which can be used in the fields of protecting storage content to prevent loss, error detection of instruments and redundant codes, etc., and can solve the problems of data retention time leakage and the like

Inactive Publication Date: 2013-04-24
MITSUBISHI ELECTRIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] However, this flash ROM is configured to record data values ​​by confining electric charge into the device, so a phenomenon called "leakage" may occur due to variations in the data retention time of each memory cell, the influence of noise, etc.

Method used

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  • Memory control device and memory control method
  • Memory control device and memory control method
  • Memory control device and memory control method

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Embodiment approach

[0016] FIG. 1 is a configuration diagram of a memory control device according to an embodiment of the present invention, and is a diagram for explaining the operation of the CPU 1 at startup. In addition, FIG. 2 is a configuration diagram of the memory control device according to the embodiment of the present invention, and is a diagram for explaining the operation when the flash ROM 4 is written or erased.

[0017] In the following description, the configuration of the memory control device will be described first, and then the operation when the CPU 1 starts up and the operation when writing data in the flash ROM 4 is performed will be described.

[0018] In FIG. 1 and FIG. 2, the main structure of the memory control device of this embodiment includes CPU1, flash ROM4 (hereinafter simply referred to as "ROM4"), and address line switching between the address bus 2 of CPU1 and ROM4. 5 (first switcher), decoder 7, and data line switcher 6 (second switcher).

[0019] CPU1 is us...

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Abstract

A memory control device is provided with: a CPU (1); a flash ROM (4) for recording therein first information which has been subjected to an error correction encoding process and second information which has not been subjected to the error correction encoding process; an address line switch (5) which switches between a first path for interconnecting an address bus (2) and the ROM (4) so as to enable the CPU (1) to read the first information recorded in the ROM (4) and a second path for interconnecting the address bus (2) and the ROM (4) so as to enable erasure, write and read of the second information recorded in the ROM (4); a decoder (7) which subjects the first information recorded in the ROM (4) to error correction and decoding; and a data line switch (6) which switches between a third path for interconnecting the decoder (7) and a data bus (3) so as to transmit the information decoded by the decoder (7) to the data bus (3) and a fourth path for interconnecting the ROM (4) and the data bus (3) so as to enable erasure, write and read of the second information recorded in the ROM (4).

Description

technical field [0001] The present invention relates to a memory control device and a memory control method using an electrically rewritable nonvolatile memory (“flash ROM” or “EEPROM: Electrically Erasable Programmable ROM”). Background technique [0002] In recent years, a flash ROM is generally mounted as a recording medium for an operating system (OS), application software, and the like in a memory control device that performs various controls by a CPU (Central Processing Unit). This flash ROM has the following features. (1) The data is retained even when the power is turned off. (2) Before writing data, it is necessary to erase the writing area. (3) Data erasure needs to be performed in predetermined block units for each device, and is performed by supplying signals in steps specified by the data pins of the device. (4) Writing of data is carried out by supplying signals according to the procedure specified by the data pin of the device. [0003] However, this flash...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/16
CPCG06F11/1417G06F11/10G06F11/1008
Inventor 重枝哲也
Owner MITSUBISHI ELECTRIC CORP