Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Manufacturing method of array substrate, array substrate and display device

A technology of an array substrate and a manufacturing method, applied in the fields of array substrates and display devices, can solve the problems affecting production efficiency, high exposure energy, and reduce exposure speed, and achieve the effects of improving production efficiency, increasing exposure speed, and reducing exposure energy.

Active Publication Date: 2016-01-06
BOE TECH GRP CO LTD +1
View PDF5 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when making the via holes on the planarization layer, such as the via holes connecting the pixel electrode and the TFT drain electrode, or the via holes in the binding area of ​​the driving circuit, etc., it is necessary to expose the planarization layer. The layer is relatively thick. In order to obtain the expected via hole size, higher exposure energy is required, which reduces the exposure speed and affects production efficiency.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Manufacturing method of array substrate, array substrate and display device
  • Manufacturing method of array substrate, array substrate and display device
  • Manufacturing method of array substrate, array substrate and display device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0039] In order to make the technical problems, technical solutions and advantages to be solved by the present invention clearer, the following will describe in detail with reference to the drawings and specific embodiments.

[0040] An embodiment of the present invention provides a method for manufacturing an array substrate, including: forming a pad layer on the array substrate, the pad layer is located under the planarization layer of the array substrate and corresponds to the position of the via hole in the planarization layer , wherein, the planarization layer is formed of hot-melt material. The hot-melt material is a material that has fluidity when heated to a certain temperature.

[0041] Specifically, the manufacturing method of the array substrate includes:

[0042] A base substrate is provided, a TFT is formed on the base substrate; a planarization layer is formed above the TFT, and a via hole is formed on the planarization layer; a pad layer is formed on the array ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A method for fabricating an array substrate, an array substrate and a display device are provided. The method for fabricating the array substrate includes: forming a spacer layer on the array substrate, the spacer layer is disposed under a planarized layer and corresponds to a location of a via hole in the planarized layer, wherein the planarized layer is formed of a hot melt material.

Description

technical field [0001] The present invention relates to the field of display technology, in particular to a manufacturing method of an array substrate, an array substrate and a display device. Background technique [0002] In the manufacturing process of the array substrate, a planarization layer is usually formed before the formation of the pixel electrodes to reduce the level difference on the substrate, making the formation of the pixel electrodes easier and reducing defects. The parasitic capacitance formed between them, the planarization layer is generally made into a thicker layer. However, when making the via holes on the planarization layer, such as the via holes connecting the pixel electrode and the TFT drain electrode, or the via holes in the binding area of ​​the driving circuit, etc., it is necessary to expose the planarization layer. The layer is relatively thick, in order to obtain the expected size of the via hole, a higher exposure energy is required, which...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/77H01L27/12
CPCH01L27/124H01L27/1218H01L27/1248H01L27/1259H01L29/66765H01L29/78678
Inventor 魏小丹张兴强陆忠张同局
Owner BOE TECH GRP CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products