Bias voltage generating circuit and memory of line decoder

Abstract

The invention discloses a bias voltage generating circuit and a memory of a line decoder. The bias voltage generating circuit of the line decoder is suitable for providing a first bias voltage and a second bias voltage to the line decoder. The bias voltage generating circuit of the line decoder comprises a high voltage detecting unit, a level shifting unit, a first driving unit and a second driving unit, wherein the high voltage detecting unit is suitable for detecting the power supply voltage of the line decoder and outputting a detection control signal; the level shifting unit is suitable for receiving the detection control signal and outputting a driving signal under the control of the detection control signal; the first driving unit is used for providing the first bias voltage under the control of the detection control signal; and the second driving unit is used for providing the second bias voltage under the control of the detection control signal. According to the technical scheme of the bias voltage generating circuit of the line decoder, the first bias voltage and the second bias voltage are respectively output through two driving units, so that the power loss in the process that a memory is subjected to erasure operation is reduced.

Description

technical field [0001] The invention relates to the technical field of memory, in particular to a bias voltage generating circuit of a row decoder and a memory. Background technique [0002] The storage unit of the memory (for example, flash memory Flash Memory) usually includes four leads: bit line (BL, Bit-Line), word line (WL, Word-Line), source line (SL, Source-Line) and baseline (SBL, Sub-Line), which are respectively coupled to the drain, gate, source and base of the MOS transistor. Generally, when performing an erase operation on a memory, a row decoder is required to apply a high voltage to a word line connected to a memory cell that performs an erase operation, and to apply a high voltage to a word line connected to a memory cell that does not perform an erase operation. Zero voltage bias voltage. [0003] figure 1 It is a schematic diagram of a circuit structure of an existing row decoder. refer to figure 1 , the row decoder includes a control signal generatio...

AI Technical Summary

Problems solved by technology

[0010] The invention solves the problem of large power loss in the process of erasing the memory in the prior art

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