Fractional phase-locked loop and its operation method

Abstract

A kind of fractional multiple phase-locked loop comprises: frequency discrimination phase detector module, is used for receiving a first frequency and a second frequency from a feedback path; Phase coarse adjustment module, is used for receiving a coarse adjustment phase component and from An output signal of a frequency divider module in the feedback path, and perform a phase coarse adjustment operation according to the coarse adjustment phase component and the output signal; the phase fine adjustment module is used to perform a phase fine adjustment operation, by receiving a fine adjustment phase component and the phase coarse adjustment result to generate the second frequency, the phase fine adjustment module eliminates most or all of the quantization noise that occurs during the phase coarse adjustment to reduce the net phase noise of the frequency divider module; and the segmentation module, It is used for receiving a control signal, and generating the coarse phase component and the fine phase component for providing to the phase fine adjustment module and the phase coarse adjustment module according to the control signal.

Description

technical field [0001] The present invention relates to a phase-locked loop, in particular to a segmented fractional phase-locked loop and an operating method thereof. Background technique [0002] For a traditional integer multiple phase-locked loop (PLL), if the accuracy of the output frequency is required to be finer, one of the methods is to pre-divide the input frequency to reduce the reference frequency. Since the output frequency is an integer (N) multiple of the input frequency, a slower reference frequency yields finer frequency accuracy. Using this method reduces the maximum achievable PLL bandwidth because the loop bandwidth should not exceed much more than 10% of the reference frequency. Reducing the loop bandwidth sacrifices the phase noise of the VCO and increases routing area due to the need for larger capacitors in the loop filter. Another way to obtain finer frequency accuracy in an integer PLL is to increase the output frequency and then divide the result...

AI Technical Summary

Problems solved by technology

However, if the split-phase generation circuit (phase interpolator, delay line, or other components) has non-idealities (mismatch, gain error, or any other effect), then the split-phase generation circuit will inevitably introduce spurs into the PLL in the system

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