Semiconductor device and manufacture method thereof

Abstract

Provided are a semiconductor device with an electrostatic discharge (ESD) protective module, and a manufacture method of the semiconductor device with the ESD protective module. According to the semiconductor device with the ESD protective module, the ESD protective module is manufactured between source electrode metal and grid electrode metal, the ESD protective module is composed of a first portion close to one side of the source electrode metal, a second portion close to one side of the grid electrode metal, and a middle portion arranged between the first portion and the second portion, the whole thickness of the ESD protective module reduces from the middle portion respectively to the first portion and the second portion, and the whole ESD protective module is enabled to be in an embossed shape. Due to the fact that the thickness of the ESD protective module is reduced at the positions close to the grid electrode metal and the source electrode metal, interlayer through holes between metal layers and a substrate of the semiconductor device and between the metal layers and the ESD protective module can be formed in the same processing step.

Description

technical field [0001] Embodiments of the present disclosure relate to a semiconductor device, and in particular, to a semiconductor device with an electrostatic protection module and a manufacturing method thereof. Background technique [0002] Semiconductor devices such as Metal Oxide Semiconductor Field Effect Transistor (MOSFET), Junction Field Effect Transistor (JFET) and Double Diffused Metal Oxide Semiconductor Field Effect Transistor (DMOS) have been widely used in the electronics industry. Generally, in order to prevent electrostatic discharge (ESD) from causing damage to the gate oxide layer of semiconductor devices such as MOSFET, JFET, DMOS, etc., an electrostatic discharge (ESD) protection module can be coupled between the gate and source of these semiconductor devices to When the voltage generated by electrostatic discharge (ESD) is higher than a certain value (for example, the value can be set to be lower than the breakdown voltage value of the gate oxide laye...

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Problems solved by technology

These interlayer vias are generally formed in the same process step, for the interlayer vias 22 that respectively couple the source metal 18 and the gate metal 17 to the polysilicon layer 19 of the ESD protection module 12 3 and 22 4 , due to its height (on the step 23) and the interlayer vias 22 that couple the source metal 18 and gate metal 17 to the source region 16 and gate region 15 of the MOSFET 11, respectively 2 ,twenty two 1 There is a large difference in height (step 23), so it will be difficult to make

For example, if these interlayer via holes (22 1 ,twenty two 2 ,twenty two 3 and 22 4 ), then when the focal depth (focal depth) of the photoresist patterning is certain, the greater height of the step 23 will have a greater impact on the photoresist patterning on the step 23, so that the photoresist patterning on the step 23 Through hole 22 3 and 22 4 Difficult to precisely form or even impossible to open, especially when via holes are required 22 3 and 22 4 When the critical dimension of the opening is small

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