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Real-time dynamic memory manager achieving method for multi-core processor

A multi-core processor, real-time dynamic technology, applied in the direction of memory address/allocation/relocation, multiprogramming device, resource allocation, etc. sexual effect

Active Publication Date: 2013-06-19
SHENYANG GOLDING NC & INTELLIGENCE TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] In order to overcome the problem that in multi-core real-time systems, concurrent tasks interfere with each other through shared Cache to reduce the real-time performance of the system, the present invention implements a real-time dynamic memory manager for multi-core real-time systems

Method used

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  • Real-time dynamic memory manager achieving method for multi-core processor
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  • Real-time dynamic memory manager achieving method for multi-core processor

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Embodiment Construction

[0025] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

[0026] The basic contents of the present invention are: establishing a real-time dynamic memory management model based on page coloring technology, establishing a memory management method for an independent area, establishing a memory management method for a shared area, and establishing a high-speed communication mechanism between tasks based on Cache.

[0027] Using the page coloring technology, the division of the shared Cache in the multi-core CNC system is realized by designing a real-time dynamic memory manager and related algorithms.

[0028] 1 page coloring technique

[0029] Page coloring is a technique that divides the shared cache by controlling the allocation of physical pages. In general-purpose processors such as X86, the page table segment in the physical address and the Cache group number segment in the Cache address have over...

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Abstract

The invention relates to a real-time dynamic memory manager for a multi-core real-time system, in particular to a real-time dynamic memory manager achieving method for multi-core processor. Cache shared by a physical memory and the multi-core processor is divided into a monopoly area, a shared area, a communication area and a non-real-time area by the page coloring technique, spare page management systems are respectively built for the monopoly area and the shared area, the communication area is packed by various synchronous mechanisms to achieve high-speed communication between tasks based on Cache, and the non-real-time area is managed by a host operation system. The real-time dynamic memory manager achieving method for the multi-core processor divides a memory and the Cache into a plurality of independent areas, prevents high priority hard real-time tasks from being interfered by other tasks through the Cache and improves system real time performance and stability. Thus, a high speed communication mechanism based on tasks of the Cache is achieved to further improve system real time performance.

Description

technical field [0001] The invention relates to a real-time dynamic memory manager for a multi-core real-time system, in particular to a method for realizing the real-time dynamic memory manager oriented to a multi-core processor. Background technique [0002] With the rapid development of real-time systems, a single processor chip can no longer meet the demand for computing bandwidth of real-time systems. Multi-core processors with low cost and strong computing power will be widely used in high-end real-time systems. But the special structure of the multi-core processor will restrict the real-time performance of the system. This poses new challenges to the design of real-time systems, especially the design of real-time operating systems. In a multi-core processor, there are hardware resources shared by multiple cores, such as shared Cache and front-side bus. Concurrent tasks will interfere with each other through these shared resources, reducing each other's real-time pe...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/50G06F12/02
Inventor 于东秦承刚吴文江董磊陈龙
Owner SHENYANG GOLDING NC & INTELLIGENCE TECH CO LTD
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