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Semiconductor Package Structure

A packaging structure, semiconductor technology, applied in the direction of semiconductor devices, electrical solid devices, electrical components, etc., can solve the problem of reducing the luminous efficiency of the overall packaging structure, and achieve the effect of the best light output efficiency

Active Publication Date: 2015-11-25
GENESIS PHOTONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this way, when the bonding wire is arranged on the bonding wire pad, the bonding wire will absorb the light emitted by the light-emitting diode, thereby reducing the luminous efficiency of the overall package structure

Method used

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  • Semiconductor Package Structure
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Experimental program
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Embodiment Construction

[0048] Figure 1A It is a schematic cross-sectional view of a semiconductor package structure according to an embodiment of the present invention. Figure 1B for Figure 1A A schematic top view of the relative relationship among the light-emitting diode chip, the pad and the conductive connector. Please also refer to Figure 1A and Figure 1B , in this embodiment, the semiconductor package structure 100a includes an insulating substrate 110 , a patterned conductive layer 120a , a light emitting diode chip 130a and a conductive connector 140 .

[0049] In detail, the insulating substrate 110 has an upper surface 112 , wherein the upper surface 112 can be divided into an element disposition area 113 and an element bonding area 115 outside the element arrangement area 113 . The patterned conductive layer 120 a is disposed on the insulating substrate 110 and located on the upper surface 112 . The patterned conductive layer 120a includes a plurality of lines 122a and at least one...

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Abstract

A semiconductor package structure includes an insulating substrate, a patterned conductive layer, a light emitting diode (LED) chip and a conductive connection part. The insulating substrate has an upper surface divided into an element configuration region and an element bonding region. The patterned conductive layer includes plural circuits located in the element configuration region and at least one bonding pad located in the element bonding region. The LED chip is flip chip bonded on the patterned conductive layer and electrically connected to the circuits. The conductive connection part has a first end point electrically connected to the bonding pad and a second end point electrically connected to an external circuit. The bonding pad and a corner of the LED chip are disposed correspondingly. A horizontal distance between an apex of the corner and the first end point of the conductive connection part is greater than or equal to 30 micrometers.

Description

technical field [0001] The present invention relates to a semiconductor element, and in particular to a semiconductor packaging structure. Background technique [0002] The purpose of chip packaging is to protect the bare chip, reduce the density of chip contacts and provide good heat dissipation for the chip. A common packaging method is to mount the chip on a carrier board by wire bonding or flip chip bonding, so that the contacts on the chip can be electrically connected to the package carrier board. Therefore, the contact distribution of the chip can be reconfigured by the package substrate to conform to the contact distribution of the external components of the next level. [0003] However, currently, when a package substrate suitable for flip-chip bonding is directly converted into a package substrate suitable for wire bonding, the position of the wire bonding pad is adjacent to the side surface of the chip. That is to say, if the chip is a light-emitting diode chip,...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L33/62
CPCH01L33/62H01L33/46H01L2224/48091H01L2924/00014
Inventor 苏柏仁吴志凌黄逸儒施怡如
Owner GENESIS PHOTONICS