Method and system of data acquisition and storage

Abstract

The invention belongs to the technical field of data acquisition and storage, in particular to a system of data acquisition and storage. The system of the data acquisition and storage comprises a filed programmable gate array (FPGA) chip, an analog to digital converter (ADC) component, a clock signal module and a first input first output (FIFO) system, wherein the FIFO system is realized in the FPGA chip. The FIFO system comprises a storage selective channel module and an FIFO write clock which are mutually connected. The FIFO write clock is remained to be in accordance with the clock signal module. The FPGA chip can drive the ADC component to collect analog signals. The clock signal module is connected with the ADC component. The output end of the ADC component is connected with the input end of the FIFO system. Compared with the prior art, the method and the system of the data acquisition and storage can utilize the FIFO system to store conversion results of the ADC component. Compared with the random access memory (RAM), the method and the system of the data acquisition and storage have a faster processing speed, and read-write is more convenient. The method and the system of the data acquisition and storage can effectively avoid the occurrence of 'race hazards' due to the fact that the storage selective channel module is set.

Description

Technical field [0001] The invention belongs to the technical field of data acquisition and storage, and in particular relates to a system and method for data acquisition and storage based on FPGA. Background technique [0002] Now is the era of digitization. In real life, many continuous analog signals must first undergo discrete serialization processing to become discrete digital quantities, and then processed by computer or electronic technology. ADC analog-to-digital converters were invented to solve this problem. of. The storage of digital quantities is also a top priority. Data storage systems in the prior art generally use random access memory (RAM), which has slow processing speed and is not very convenient to read and write. [0003] For this reason, some people have developed FIFO (that is, the first-in first-out queue) to store the results obtained by ADC conversion, but the previous design is prone to "competitive risk". Among them, competition means that in a combin...

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Problems solved by technology

The reason for the risk of competition is that due to the existence of delay time, when an input signal is transmitted through multiple paths and rejoins a certain gate, due to the different stages of gates on different paths, or the difference in delay time of gate circuits, resulting in The time to reach the rendezvous point is first and then later, resulting in instantaneous error output

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