A verification method of sram type fpga synchronous switching noise

Abstract

The invention provides an SRAM type FPGA synchronous switch noise verification method which is achieved based on an SRAM type FPGA synchronous switch noise verification device. The device comprises a PC machine, an FPGA socket, a signal input unit and an adjustable load capacitor. The SRAM type FPGA synchronous switch noise verification method includes relations among the maximal synchronous switch quantity in single I / O-BANK, mutual influence of synchronous switch noise among different I / O-BANKs, synchronous switch noise, I / O port quantity, output turning speed, clock frequencies, interfered line positions and the load capacitor. During a verification process, different test files are configured for FPGA to be verified through the PC machine, under the condition of different clock frequencies and loads, interference noise on sensitive signal lines in FPGA to be verified is tested to achieve verification of synchronous switch noise signal integrity.

Description

technical field [0001] The invention relates to a SRAM type FPGA synchronous switch noise verification method, which belongs to the technical field of FPGA application verification. Background technique [0002] With the development of semiconductor technology, the integration level of SRAM FPGA is constantly increasing. Therefore, on the one hand, the I / O ports of the FPGA are increasing and the distribution is more dense, making it easier for the I / O to interfere with each other; on the other hand, due to power consumption and heat dissipation, the operating voltage of the FPGA becomes lower, making the I / O more sensitive to disturbances. However, in the current high-performance FPGA system design, hundreds of I / Os of the FPGA often change in parallel at the same time under low voltage conditions, which is very easy to generate synchronous switching noise. Therefore, the impact of simultaneous switching noise on system design is critical. Contents of the invention [...

AI Technical Summary

Problems solved by technology

In the current high-performance FPGA system design, FPGA I / Os often have hundreds of I / Os changing in parallel at the same time under low voltage conditions, which is very easy to generate synchronous switching noise.

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