Modified Xilinx FPGA power-on reset circuit

Abstract

The invention provides a modified Xilinx FPGA power-on reset circuit. The modified Xilinx FPGA power-on reset circuit comprises a PROM, an FPGA chip, a resistor R1, a resistor R2, a capacitor C1, a capacitor C2, a Schmitt trigger and a phase inverter. Global reset signals need to be led from the outside so that software can have fixed working start points after power-on configuration of the FPGA is finished. After the modified Xilinx FPGA power-on reset circuit is powered on, the FPGA chip reads configuration information from the PROM, initialization setting is conducted, a configuration process of the FPGA is finished when a DONE signal end in the FPGA chip changes into a high electric level, a high electric level signal of the DONE signal end generates a global reset signal through an RC delay reset circuit, then the global reset signal is sent to an MRST end of the FPGA, and the FPGA chip starts to work. According to the modified Xilinx FPGA power-on reset circuit, in hardware circuit design, a DONE signal is subjected to RC delay, is reshaped through the Schmitt trigger, then passes through a primary phase inverter, and is used as global reset input of the software.

Description

technical field [0001] The invention relates to an improved power-on reset circuit system applied to Xilinx FPGA. Background technique [0002] 1. Analysis of FPGA configuration startup process: [0003] Xilinx's FPGA chip is a volatile device based on the SRAM type process, and the circuit function is realized by the bits stored in the SRAM type configuration register. After the FPGA chip is powered on, it must read the configuration information from the PROM before it can work normally. [0004] The configuration process includes 5 stages: initialization, clearing configuration memory, loading configuration data, CRC check, START-UP. After the FPGA is powered on, if the power supply of the FPGA device meets the requirements, it will automatically initialize. After the initialization process is completed, the device will set the INIT and DONE signals to low level and start to clear the configuration memory at the same time. After clearing the configuration memory, the I...

AI Technical Summary

Problems solved by technology

[0010] The problem with using the GSR pin as the global reset input of the software is that the delay of the reset signal line reaching each flip-flop is not the same, and it is very possible that the difference is tens of nanoseconds on a large

Images