An Instruction Cache Memory Based on Flag Access Trace

Abstract

The invention relates to an instruction cache memory (an instruction Cache) based on an access trace of a zone bit. The instruction cache memory comprises a trace information table, a trace information maintenance circuit and a control circuit, wherein the depth of the trace information table is equal to the line number of the instruction Cache, each line is used for storing a trace information bit which expresses whether the access trace of a corresponding line to a mark memorizer exists or not, the trace information maintenance circuit outputs an overflow control signal according to an input branch direction, an input branch target address, an instruction taking address and a program segment address range in the trace information maintenance circuit, the overflow control signal expresses whether the instruction taking address or the branch target address is in the program segment address range or not, and the control circuit is used for controlling the reading for the mark memorizer according to the trace information bit and conducting maintenance on the trace information table according to the overflow control signal. According to the instruction Cache, recorded mark bit access information is utilized to conduct hit detection on the instruction Cache in advance in a program executing process, unnecessary mark memorizer access is eliminated, and power consumption of the instruction Cache is effectively reduced.

Description

technical field [0001] The invention relates to an instruction cache memory based on flag bit access trace. Background technique [0002] With the rapid development of semiconductor process technology, the performance and integration of embedded processor chips have been greatly improved, and the resulting power consumption problem has become increasingly serious. As an important part to bridge the speed gap between the processor core and the main memory, the instruction cache memory (instruction cache) consumes a lot of power because of its high access frequency. Therefore, effectively reducing the power consumption of the instruction cache is of great significance for the design of low-power embedded processors. [0003] The structure of the traditional instruction cache using the direct mapping method is as follows: figure 1 As shown, it is mainly composed of flag (tag) memory, data (data) memory and status bit (state). When the processor core accesses the instruction ...

AI Technical Summary

Problems solved by technology

[0006] (1) This technology is closely combined with the branch target buffer. When the branch prediction and the update of the program execution history information occur at the same time, the processor pipeline will stall, resulting in a decrease in processor performance;

[0007] (2) When the instruction cache is missing, all the program execution history information needs to be cleared, resulting in the processor being unable to use the already recorded effective history information to eliminate unnecessary flag memory access during program execution, thus reducing the program execution history. efficient use of information;

[0008] (3) For embedded processors that do not use a branch prediction mechanism, building a branch predictor requires a large hardware cost, and the branch predictor itself also consumes some energy

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