Multi-wafer encapsulating structure
A packaging structure, multi-chip technology, applied in electrical components, electrical solid-state devices, circuits, etc., can solve problems such as high equipment and technical cost requirements, high process precision requirements, and increased process difficulty, so as to avoid bump generation. And flip-chip technology, reducing the difficulty of the process, the effect of reducing the cost
Inactive Publication Date: 2015-06-03
聚芯芯片科技(常州)股份有限公司
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Problems solved by technology
[0006] This kind of packaging structure improves the packaging density, but because the generation of bumps requires a wafer-level process, the equipment and technical costs are relatively high, and the flip-chip technology has high requirements for the precision of the chip (DIE Bond) process, which increases the The process is difficult and the cost is high
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no. 1 Embodiment
[0026] According to the first specific embodiment of the present invention, a multi-chip packaging structure is disclosed, Figure 1C is a schematic cross-sectional view of the multi-chip package structure, Figure 1D is a schematic diagram of the top surface of the substrate in the multi-chip package structure.
[0027] First, please refer to the attached Figure 1C As shown, the multi-chip package structure is shown as a preferred implementation structure of the present invention. The windowed multi-chip stacked package of the present invention mainly includes a substrate 10, a first chip 7, and a second chip 15. A plurality of external terminals—solder balls 9 .
[0028] It should be noted that the substrate 10 satisfies the general concept of a circuit board. According to common understanding, it has and only two sides, which are represented as two board sides.
[0029] In order to be able to clearly distinguish in the following content, the substrate 10 has a first sur...
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The invention discloses a multi-wafer encapsulating structure which comprises a substrate with two opposite faces, and two wafers which are installed on the substrate and electrically connected with a substrate circuit. A window is respectively formed in two opposite end portions of the substrate, one of the wafers is arranged on each face, one face is a bonding face, and the other face is an external terminal face. Therefore, the wafer located on the bonding face is directly bonded through a bonding line, and the other wafer is bonded through a bonding line which penetrates through the windows. By means of the multi-wafer encapsulating structure, on the premise that encapsulated body wafer density is improved, and technology realizing difficulty is comparatively low.
Description
technical field [0001] The invention relates to a multi-chip packaging structure. Background technique [0002] With the vigorous development of the electronic industry and the continuous evolution of electronic technology, electronic products are also designed towards the trend of light, thin, short and small. With the increasing demand for miniaturization and high-operation technology, multiple chips will be integrated in one package structure to achieve more than double the capacity or systemic functional requirements. For example, in the previous multi-chip stack package structure, it is Multiple chips are stacked and encapsulated in an encapsulation material. [0003] In general, among the known multi-chip packaging technologies, such as Figure 1A The structure shown is that two chips are stacked in parallel, which mainly includes a substrate 10', a first chip 1' and a second chip 14' stacked on the substrate 10', and a plurality of bonding wires 12' for the first Th...
Claims
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IPC IPC(8): H01L25/00H01L23/31H01L23/498
CPCH01L2224/32145H01L2224/32225H01L2224/45144H01L2224/48091H01L2224/48227H01L2224/4824H01L2224/73215H01L2224/73265H01L2924/15311H01L2924/181
Inventor 栗振超户俊华孟新玲刘昭麟
Owner 聚芯芯片科技(常州)股份有限公司