Shielding structure with ebg, 3D encapsulation structure and preparation method thereof

A technology of packaging structure and shielding structure, which is applied in the direction of semiconductor/solid-state device parts, semiconductor devices, electrical components, etc., can solve the problems of large vertical size, unfavorable package miniaturization, and long vertical interconnection distance between sensitive chips and interfering chips. To achieve a convenient method, the effect of suppressing noise

Active Publication Date: 2016-02-03
NAT CENT FOR ADVANCED PACKAGING CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the POP package, the vertical interconnection distance between the sensitive chip and the interfering chip is far away, and the near-field coupling problem is not too serious, but the vertical size of this package is relatively large, which is not conducive to the miniaturization of the package.

Method used

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  • Shielding structure with ebg, 3D encapsulation structure and preparation method thereof
  • Shielding structure with ebg, 3D encapsulation structure and preparation method thereof
  • Shielding structure with ebg, 3D encapsulation structure and preparation method thereof

Examples

Experimental program
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Effect test

Embodiment 1

[0026] like figure 1 In the shown 3D packaging structure, the bare chips 109 and 110 are bonded on the interconnection substrate 112 by flip-chip bonding, and filled with underfill glue to protect the flip-chip bumps 111 . The individual shielding device 103 with the EBG structure is fixed on the bare chips 109 and 110 with an adhesive. The shielding device 103 includes a support plate 107, a first metal plane 106 etched with a periodic EBG structure, an insulating layer 105, and a second metal plane 104, wherein the unit shape, number and even structural deformation of the periodic EBG structure suppress noise as required Frequency band decision. The support plate can be a variety of substrates such as silicon-based or glass-based, organic substrates, and even ceramic substrates. The insulating material of the corresponding insulating layer 105 may be SiO 2 、Si 3 Ni 4 , organic substrate materials or ceramic materials and other materials. The bare chip 101 is fixed on t...

Embodiment 2

[0037] like figure 2 In the shown 3D packaging structure, the bare chip 209 is bonded on the interconnection substrate 212 by wire bonding. A separate shielding device 214 with an EBG structure is fixed on the bare chip 209 with an adhesive, and the shielding device 214 is prepared using a flexible substrate, including a first metal plane 217, an insulating layer 216, and a second metal layer etched with a periodic structure. Plane 215. Among them, the unit shape, quantity and even structural deformation of the periodic structure are determined according to the noise frequency band to be suppressed. The bare chip 201 is fixed on the shielding device 214 with an adhesive, and bonded to the interconnection substrate 212 by wire bonding. The bonding wire 202 is made of various materials such as gold wire, copper wire or aluminum wire. Potting compound 208 such as plastic encapsulant is filled between the 3D stacked bare chips 201 and 209 and the shielding device 214 to fix the...

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PUM

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Abstract

The present invention provides a shielding structure with EBG, a 3D packaging structure and a preparation method thereof. The shielding structure with EBG includes an insulating layer and at least two metal planes; wherein, at least one metal plane is etched with a periodic EBG structure; An insulating layer is arranged between the metal planes. The method for preparing an EBG shielding structure includes preparing at least one metal plane; preparing an intermediate insulating layer; and preparing at least one metal plane with a periodic EBG structure. The 3D packaging structure includes a shielding structure with EBG, a bare chip, and an interconnection substrate; the bare chip is bonded on the interconnection substrate, and the bare chip is connected to the shielding structure. Also provided is a preparation method for 3D encapsulation. The invention can effectively reduce the near-field coupling problem between chips in the vertical 3D interconnection package.

Description

technical field [0001] The invention relates to the technical field of microelectronic packaging, in particular to a shielding structure with EBG (Electromagnetic Band Gap, EBG), a 3D packaging structure and a preparation method thereof. Background technique [0002] With the rise of communication electronics, people's demand for miniaturized and high-sensitivity modules or systems is getting higher and higher, and the requirements for signal quality are becoming more and more stringent. High-density integration technologies, such as System-in-Package (SiP) technologies, have developed rapidly, but miniaturized integrated packaging of mixed-signal multi-chip systems has become one of the technical difficulties in this field. [0003] The frequency of digital signals continues to rise, and the rising / falling edges become more and more jittery. The high-frequency components of digital signals have an increasing impact on sensitive circuits such as analog or RF chips. The sens...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/552
CPCH01L2924/15311H01L2224/16225H01L2224/32145H01L2224/32225H01L2224/48091H01L2224/48227H01L2224/73204H01L2224/73253H01L2924/3025H01L2924/00014H01L2924/00
Inventor 李君万里兮郭学平
Owner NAT CENT FOR ADVANCED PACKAGING CO LTD
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