memory address translation

Abstract

The present invention includes devices, systems and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a plurality of records, where each record includes a plurality of entries, where each entry includes a physical address and a logical address corresponding to a sector of data stored in the array. The controller includes a second table having a plurality of records, where each record includes a plurality of entries, where each entry includes a physical address and a logical address corresponding to a record in the first table. The controller also includes a third table having a plurality of records, where each record includes a plurality of entries, where each entry includes a physical address and a logical address corresponding to a record in the second table.

Description

technical field [0001] The present disclosure relates generally to semiconductor memory devices, methods and systems, and more particularly to memory address translation. Background technique [0002] Memory devices are often provided as internal semiconductor integrated circuits and / or external removable devices in computers or other electronic devices. There are many different types of memory including random access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change Random Access Memory (PCRAM) and Flash Memory. [0003] Flash memory devices can be used as volatile and non-volatile memory for a wide range of electronic applications. Flash memory devices typically use one-transistor memory cells with high memory density, high reliability, and low power consumption. Flash memory devices can often have a "NAND" or "NOR" memory array architecture (the so-called logical form in which the b...

AI Technical Summary

Problems solved by technology

However, the size (e.g., the amount of stored data) of the address mapping table used in the previous FTL method may be fixed

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