Layout design rule check file verification graphics library and establishment method thereof

Abstract

The invention discloses a layout design rule detection file verification graphics library and an establishment method thereof. The layout design rule check file verification graphics library comprises a minimum line width, a minimum space, a minimum distance enclosing another graphic layer by one graphic layer, a minimum distance extending to another graphic layer from one graphic layer, a single-layer graph with the minimum width overlapped by two graphic layer parts, and design rule check among multilayer graphs. According to the layout design rule detection file verification graphics library provided by the invention, on one hand, the incomplete verification graph kinds due to inadequate experience of a verification engineer can be made up; on the other hand, the development cycle of establishing the verification graph can be shortened. The layout design rule detection file verification graphics library can be used for providing the reference for manually establishing the verification graphs by any layout verification engineer and can also be used for an automatic generation tool of the verification graph, directly calling a graphics library file and realizing batch production of the verification graph by using a tool to modify the basic line width, the layer and other variables.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design, in particular to a layout design rule detection file verification graphics library and a method for establishing the same. Background technique [0002] With the increasing complexity of the chip manufacturing process, more and more layers of layout requirements and more and more strict requirements for layers of graphics, the verification documents used for layout graphic design rule detection also become more and more complex. The more important it is, the accuracy and completeness of the layout design rule inspection file directly determines the product yield. [0003] The layout verification graphics library is a set of analog layout graphics library established based on the achievable requirements of the process layout and the requirements of the integrated circuit design, and is used to verify the correctness and comprehensiveness of the layout design rule file (DRC, Desig...

AI Technical Summary

Problems solved by technology

Due to the lack of experience of each engineer in process and layout, and the incomplete preparation of reference materials, it is difficult to ensure the accuracy of verification graphics and the integrity of the database, so it is difficult to ensure the correctness of design rule detection documents

Secondly, in the design rule file, there are many levels of design rules that are similar, or even just differ in value, resulting in a large amount of repetitive work and reduced efficiency

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