Field effect transistor and method of fabricating the same

Abstract

Provided is a field effect transistor including a drain region, a source region, and a channel region. The field effect transistor may further include a gate electrode on or surrounding at least a portion of the channel region, and a gate dielectric layer between the channel region and the gate electrode. A portion of the channel region adjacent the source region has a sectional area smaller than that of another portion of the channel region adjacent the drain region.

Description

technical field [0001] Example embodiments of inventive concepts relate to field effect transistors and methods of fabricating the same, and in particular, to field effect transistors having nanoscale channel regions and methods of fabricating the same. Background technique [0002] The performance of CMOS devices used in digital circuits may depend on channel switching speed and / or channel controllability through the gate electrode. For analog circuits, the current can be changed by relatively small changes in the gate voltage. As the pattern size of the two-dimensional transistor decreases, the electric field strength between the source region and the drain region will increase significantly, the hot carrier effect will be enhanced, and / or the dissipation from the source region and the drain region will increase significantly. Exclusion zones overlap each other. Due to the overlap of the depletion region, it may be difficult to control the switching of the channel region...

AI Technical Summary

Problems solved by technology

Due to the overlap of the depletion region, it will be difficult to use the electric field from the gate electrode to control the switching of the channel region

In addition, the size ratio of the depletion region around the source and drain regions relative to that of the entire channel region increases

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