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GOA (gate driver on array) circuit, array substrate, display device and driving method

A circuit and input terminal technology, which is applied in the fields of GOA circuits, display devices, and array substrates, can solve the problems of many transistors and large array substrate areas, and achieve the effect of area reduction

Active Publication Date: 2013-11-13
HEFEI BOE OPTOELECTRONICS TECH +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In the existing technology, a GOA unit usually includes 12 transistors and a capacitor. When a GOA unit drives a gate line, the GOA circuit uses many transistors and occupies a large area of ​​the array substrate.

Method used

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  • GOA (gate driver on array) circuit, array substrate, display device and driving method
  • GOA (gate driver on array) circuit, array substrate, display device and driving method
  • GOA (gate driver on array) circuit, array substrate, display device and driving method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0092] The selection signal output subunit is used to receive a source signal and output a selection signal according to the source signal;

[0093] The selection subunit receives the selection signal and N clock signals, and outputs the received clock signal according to the selection signal;

[0094] There are at least N clock signal input lines for inputting clock signals to the selection subunits.

[0095] The internal structure of the selection signal subunit can be composed of a GOA unit connected by 12 transistors and a capacitor, or an SRC cascaded register composed of thin film transistors;

[0096] The selection subunit receives N clock signals, and under the control of the selection signals, decides whether to output clock signals, and these clock signals are input to the gate lines of the array substrate where the GOA circuit is located, and the gate lines are based on the The high and low levels of the clock signal turn on or off the switch (usually a thin film t...

Embodiment 2

[0102] The selection signal output subunit includes a source signal input terminal 1, a source signal input terminal 2, a start signal input terminal, a signal output terminal 1, a signal output terminal 2, and a reset signal input terminal;

[0103] The source signal input terminal is used for inputting a first source signal;

[0104] The second source signal input terminal is used to input a second source signal;

[0105] The signal output end is connected to the selection subunit for outputting a selection signal generated according to the first source signal and the second source signal;

[0106] The start signal input end of the first GOA unit is connected to the start signal line to receive the start signal, and the reset signal input end of the first GOA unit is connected to the signal of the second GOA unit. The output terminal one is connected to receive the selection signal output by the signal output terminal one of the second GOA unit;

[0107] The start signal i...

Embodiment 3

[0113] The N clock signal input terminals are respectively connected to the N clock signal input lines for inputting clock signals;

[0114] The selection signal input terminal is used to receive the selection signal output by the selection signal output subunit;

[0115] The clock signal output end outputs the received clock signal according to the selection signal.

[0116] Such as figure 1 As shown, as a further embodiment of this embodiment:

[0117] The N=4;

[0118] The GOA unit also includes a gate line on voltage line and a gate line off voltage line; the gate line on voltage Von is always high level, and the gate line off voltage Voff is always low level;

[0119] The selection subunit includes a pull-up module, a holding module, a gate-line on-voltage input terminal connected to the gate-line on-voltage line, and a gate-line off-voltage input terminal connected to the gate-line off-voltage line ;

[0120] The pull-up module includes a first transistor T1, a seco...

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Abstract

The invention discloses a GOA (gate driver on array) circuit, an array substrate, a display device and a driving method. The GOA circuit comprises a clock signal input line and more than two cascaded GOA units. Every GOA unit comprises a selection signal output subunit and a selection subunit; the selection signal output subunit is used for receiving source signals and outputting selection signals according to the source signals; the selection subunit receives the selection signals and N clock signals and outputs the received clock signals according to the selection signals; the number of the clock signal input lines is at least N, and the clock signal input lines are used for inputting the clock signals to the selection subunits; and N is an integer larger than 2. The GOA circuit, the array substrate and a gate driving structure of the display device are ingenious, and occupied spaces are small. According to the driving method, single-point polarity inversion can be achieved, and contradiction between display effects and energy consumption can be adjusted extremely well.

Description

technical field [0001] The invention relates to the display field, in particular to a GOA circuit, an array substrate, a display device and a driving method. Background technique [0002] GOA: GateDriverOnArray - driver on array substrate. [0003] The existing GOA circuit usually includes several GOA units, and each GOA unit corresponds to a gate line. Specifically, the output end of each GOA unit is connected to a gate line, and the output end of each GOA unit is also connected to the next GOA unit. The input terminal of the unit is used to turn on the next GOA unit, and the output terminal of the next GOA unit is also connected to the reset signal input terminal of the previous GOA unit. [0004] In the existing technology, a GOA unit usually includes 12 transistors and a capacitor. When a GOA unit is corresponding to drive a gate line, the GOA circuit uses many transistors and occupies a large area of ​​the array substrate. Contents of the invention [0005] In view ...

Claims

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Application Information

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IPC IPC(8): G09G3/36G02F1/133G02F1/1362G02F1/1368
CPCG09G3/3614G02F1/133G09G3/36G09G3/3607G09G3/3659G09G3/3677G09G3/3696G09G2300/0408G09G2300/0426G09G2300/0809G09G2310/0205G09G2310/0286G09G2310/06G09G2320/0223G09G2320/0252G09G2320/0673
Inventor 黄家成何剑冯霞
Owner HEFEI BOE OPTOELECTRONICS TECH
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