Digital hardware circuit logical error diagnosis mechanism

A hardware circuit, logic error technology, applied in the field of formal verification, can solve the problems of inaccuracy, compromise between accuracy and processing capacity, limited processing capacity, etc., to achieve the effect of improving stability and reliability

Inactive Publication Date: 2013-11-20
BEIHANG UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

There are many studies on simulation-based error diagnosis methods. This type of method has good scalability and can handle large circuits, but it is not accurate enough.
Most formal diagnosis methods based on BDD are li

Method used

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  • Digital hardware circuit logical error diagnosis mechanism
  • Digital hardware circuit logical error diagnosis mechanism

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Embodiment Construction

[0017] The present invention is a diagnostic mechanism for digital hardware circuit logic errors, comprising the following processing steps:

[0018] Step 1: Filter candidate regions

[0019] According to the internal characteristics of candidate error regions, some candidate regions are selectively removed by using structural similarity. To find equivalent area pairs from the selected candidate areas, that is, possibly equivalent area pairs, you can use the method of topological sorting, that is, sorting in the order of fan-in priority, so that the previously derived internal equivalence can be It is used for the subsequent equivalence derivation process, that is, to simplify the miter circuit by replacing the equivalent area. The core step of the method is to use the incremental satisfiability algorithm to verify the equivalence of all candidate regions sequentially according to topological sorting or to prove that they are not equivalent. If a region f is a region that ha...

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PUM

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Abstract

The invention discloses an improved digital hardware circuit diagnosis mechanism. According to the digital hardware circuit diagnosis mechanism, an equivalence checking method based on satiable increment is applied to error diagnosis, certain candidate areas are excluded by means of similarity of internal structures of candidate areas, and then processing speed of error checking is improved. According to the digital hardware circuit diagnosis mechanism, the stability and reliability of design are systematically improved by means of the combination of various formalized methods such as the increment equivalence checking method, a logic simulation method and a Boolean satisfiability method.

Description

technical field [0001] The invention relates to a formal verification method belonging to a digital hardware circuit, in particular to a logic error diagnosis mechanism of a digital hardware circuit. Background technique [0002] Digital hardware circuits need to be constantly inspected and tested during the design process. Check whether the process design satisfies the given specification. Once the inspection tool finds a design error, it is necessary to diagnose and debug the design error in order to obtain a correct version that meets the design specification. When the inspection tool finds that the design specification is inconsistent with the implemented function, it is necessary to perform error diagnosis, that is, to identify or minimize the suspected error area in the design implementation, and then reduce the potential error area as much as possible through a specific algorithm, that is, the candidate area . [0003] Existing error diagnosis methods can be divided...

Claims

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Application Information

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IPC IPC(8): G06F17/50
Inventor 傅翠娇王锐栾钟治钱德沛
Owner BEIHANG UNIV
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