A wafer-level high-density wiring preparation method

Abstract

The invention relates to a wafer-level high-density wiring preparation method, which belongs to the technical field of semiconductor packaging. It includes the following process: providing a silicon wafer (100), selectively forming an electroplating seed layer I (210) on the surface of the silicon wafer (100), and depositing on the surface of the electroplating seed layer I (210) Wiring A (220), the spacing is set between adjacent wiring A (220); a dielectric layer is formed on the top and sidewall of the wiring A (220) and the sidewall of the electroplating seed layer I (210) ( 230); forming an electroplating seed layer II (310) on the surface of the silicon wafer (100) between adjacent wiring A (220), and depositing wiring B on the surface of the electroplating seed layer II (310) ( 330). The invention can reduce the difficulty of the process and avoid the bridging problem in the traditional rewiring process. At the same time, the invention prepares the wiring A first, and then prepares the wiring B, and can form a wiring pattern with a height difference, which is convenient for practical use.

Description

technical field [0001] The invention relates to a wafer-level high-density wiring preparation method, which belongs to the technical field of semiconductor packaging. Background technique [0002] With the continuous development of electronic products in the direction of light, thin, short and small, Wafer Level Chip Scale Package (WLCSP, Wafer Level Chip Scale Package) is becoming more and more popular. In wafer-level packaging, the rewiring technology is used to rearrange the input / output interfaces of the chip on the wafer surface to facilitate the final mounting. With the improvement of chip integration density and the complexity of chip functions, the chip area continues to shrink, while the input / output ports continue to increase, which makes the wiring density of the rewiring layer more and more large, and the line spacing is getting smaller and smaller. [0003] The main process of the traditional wafer-level rewiring process is as follows: firstly, a seed layer is ...

AI Technical Summary

Problems solved by technology

As the wiring density increases, the photoresist between two adjacent wirings is required to be very narrow. This narrow photoresist is not only easy to be washed away by the plating solution when electroplating wiring, but also prone to seepage. As a result, adjacent wiring bridges are short-circuited, leading to product failure and affecting product yield; and the wiring pattern of equal height also limits the actual use

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