Unlock instant, AI-driven research and patent intelligence for your innovation.

Etch first and then seal 3D system-on-chip front-mounted stacking package structure and process method

A system-level chip, etching first and sealing later technology, which is applied in semiconductor/solid-state device parts, semiconductor devices, electrical components, etc., can solve the problem that the quality of interconnection solder balls between packages is difficult to control, etc.

Active Publication Date: 2016-06-01
江苏尊阳电子科技有限公司
View PDF6 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] The purpose of the present invention is to overcome the above-mentioned shortcomings, and provide a three-dimensional system-in-package structure and process method for sealing first and then etching chips. The problem that the quality of interconnection solder balls is difficult to control

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Etch first and then seal 3D system-on-chip front-mounted stacking package structure and process method
  • Etch first and then seal 3D system-on-chip front-mounted stacking package structure and process method
  • Etch first and then seal 3D system-on-chip front-mounted stacking package structure and process method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0199] Embodiment 1, single-layer line single-chip front-mounted single-turn pins

[0200] see Figure 27 , is a structural schematic diagram of Embodiment 1 of the three-dimensional system-on-a-chip stacked package structure of the present invention, which includes a base island 1 and pins 2, and the front side of the base island 1 is provided with a conductive or non-conductive adhesive material 3 There is a chip 4, the front of the chip 4 is connected with the front of the pin 2 with a metal wire 5, and a conductive pillar 6 is arranged on the front of the pin 2, the area around the base island 1, the base island 1 The area between pin 2 and pin 2, the area between pin 2 and pin 2, the area above base island 1 and pin 2, the area below base island 1 and pin 2, and chip 4, metal line 5 and The conductive pillars 6 are all encapsulated with a molding compound 7, the molding compound 7 is flush with the top of the conductive pillars 6, and the surface of the base island 1, th...

Embodiment 2

[0254] Embodiment 2, stacked J-shaped package body

[0255] see Figure 28 , is a structural schematic diagram of Embodiment 2 of the three-dimensional system-on-a-chip stacked package structure of the present invention that is etched first and then sealed. The difference between Embodiment 2 and Embodiment 1 is that the outer corner of the package body 9 is a J-shaped pin.

Embodiment 3

[0256] Embodiment 3, stacked L-shaped package body

[0257] see Figure 29 , is a structural schematic diagram of Embodiment 3 of the three-dimensional system-on-a-chip stacked package structure of the present invention, which is etched first and then sealed. The difference between Embodiment 3 and Embodiment 1 is that the outer corner of the package body 9 is L-shaped.

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to an etch-before-seal three-dimensional system-level chip front-mounted stacking package structure and process method, which includes a base island and pins, and a chip is arranged on the front side of the base island through conductive or non-conductive materials, and the chip The front side is connected with the front side of the pin with a metal wire, and a conductive pillar is arranged on the front side of the pin, the area around the base island, the area between the base island and the pin, and the area between the pin and the pin area, the base island and the upper part of the pin, the base island and the lower part of the pin, as well as the chip, the metal wire and the conductive pillar are all encapsulated with a plastic encapsulant, and the conductive material is arranged on the top of the conductive pillar or the back of the pin. package body. The beneficial effect of the invention is that it can solve the problem that the quality of interconnected solder balls between packages is difficult to control due to the fact that the pads of the bottom substrate are lower than the plastic surface of the bottom layer of the traditional substrate packaging stack.

Description

technical field [0001] The invention relates to an etch-before-seal three-dimensional system-level chip front-mount stack package structure and a process method. It belongs to the technical field of semiconductor packaging. Background technique [0002] The traditional common PoP package stacking structure is that the bottom logic device substrate package is stacked with the top storage device substrate package, and the bottom device and the top layer device are stacked and electrically interconnected by solder ball mounting and reflow soldering. Such as Figure 81 . [0003] The above PoP (Package on Package) packaging structure has the following disadvantages: [0004] 1. The pads connecting the bottom package and the top package are located on the substrate of the bottom package, which is lower than the plastic cover of the bottom package, so the molding height of the bottom package is limited by the size of the metal solder ball on the bottom surface of the top package...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/48H01L21/56H01L23/495H01L23/31
CPCH01L23/49513H01L23/49517H01L23/49811H01L23/49816H01L23/49822H01L21/4825H01L21/4853H01L25/105H01L2224/48091H01L2224/73265H01L2224/83192H01L2224/92247H01L23/3107H01L21/561H01L21/568H01L2924/181H01L2225/1029H01L2225/1058H01L2225/1023H01L2924/00014H01L2924/00012H01L21/4828H01L21/4842H01L21/4889H01L21/565H01L23/3178H01L23/4952H01L23/49575H01L25/0657H01L25/50H01L2225/0651H01L2225/06517H01L2225/06541H01L2225/06582
Inventor 梁志忠王亚琴章春燕林煜斌张友海
Owner 江苏尊阳电子科技有限公司