Circuit and method for controlling leakage current in random access memory element
A random access memory, memory cell technology, applied in static memory, digital memory information, information storage, etc., can solve the problem that the leakage current of the bit line cannot be completely eliminated.
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[0034] Figure 4 A circuit 400 for controlling leakage current in random access memory devices incorporating an embodiment of the present invention is shown. refer to Figure 4 , the circuit 400 includes a precharge equalization circuit 402 connected to one bit line BL and another bit line BL'. The precharge equalization circuit 402 includes a first transistor 404 , a second transistor 406 and a third transistor 408 . The first transistor 404 connects a precharge voltage VEQ to the bit line BL. The second transistor 406 connects the precharge voltage VEQ to the bit line BL'. The third transistor 408 connects the bit line BL to the bit line BL'. A precharge signal EQD is used to control the first transistor 404 , the second transistor 406 and the third transistor 408 .
[0035] Figure 5 A timing diagram showing control signals when applying the circuit 400 to a DRAM device operating in a self-refresh mode in conjunction with an embodiment of the present invention. refer...
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