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16-bit parallel self-synchronous scrambler and descrambler for GFP (generic framing procedure) data frame transmission

A technology of self-synchronizing scrambling and scrambling code, applied in the field of data communication, can solve the problem of unsuitable scrambler and descrambler, and achieve the effect of reducing the working frequency, easy to implement, and simple circuit

Inactive Publication Date: 2014-01-22
TOEC TECH
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  • Description
  • Claims
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AI Technical Summary

Problems solved by technology

[0005] The circuit structure of the serial scrambler and descrambler mentioned above is simple, but if it is applied in the SDH system, it is only suitable for STM-1 (Synchronous Transmission Module), and the working line speed is below 155.52Mb / s. For STM-16 (No. Three-level synchronous transmission module) SDH signal, the rate is 2.48832Gb / s, this kind of GFP serial self-synchronous scrambler and descrambler is not suitable, it puts forward very high requirements to the integrated circuit (IC) process Therefore, it is necessary to improve the existing scrambler and descrambler technology, and design a 16-bit parallel self-synchronous scrambler / descrambler for transmitting GFP data frames, in order to meet the requirements of SDH system Require

Method used

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  • 16-bit parallel self-synchronous scrambler and descrambler for GFP (generic framing procedure) data frame transmission
  • 16-bit parallel self-synchronous scrambler and descrambler for GFP (generic framing procedure) data frame transmission
  • 16-bit parallel self-synchronous scrambler and descrambler for GFP (generic framing procedure) data frame transmission

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Embodiment Construction

[0019] In order to understand the present invention more clearly, describe the present invention in detail in conjunction with accompanying drawing and embodiment:

[0020] According to the provisions in the general framing procedure G.7041 / Y1303, according to figure 1 , figure 2 As shown, for the sequence X 43 The scrambling and descrambling circuit implemented by +1, each output value is the result of the modulo 2 addition of the input value and the output value 43 clocks ago, and outputs a scrambling code value at each line speed clock, which can be output in 43 clock cycles 43 scrambled signals.

[0021] For the first clock cycle, the output of each D flip-flop is:

[0022] D. i (t+1)=D i-1 (t), i= 1,2,...,42; D i (t+1)=X(t) XOR D 42 (t), i=0

[0023] For the 8th clock cycle, the outputs of the individual D flip-flops are:

[0024] D. i (t+8)=D i-8 (t), i= 8,9,...,42; D i (t+8)=X (t+7-i) XOR D 35+i (t), i=0,1,...,7

[0025] By analogy, fo...

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Abstract

The invention relates to a 16-bit parallel self-synchronous scrambler and descrambler for GFP data frame transmission. A scrambler circuit comprises 43 D flip flops (D0...D42) and 16 Exclusive-OR gates, wherein the 43 D flip flops (D0...D42) and the 16 Exclusive-OR gates are interleaved and connected in series sequentially; values obtained through xor between output signals (Q42...Q27) of higher 16-bit D flip flops (D42...D27) and 16-bit input signals serve as input signals of lower 16-bit D flip flops (D15...D0); and output signals of the lower 16-bit D flip flops (D15...D0) form a 16-bit parallel scrambling sequence. A descrambler circuit comprises 43 D flip flops (D0...D42) and 16 Exclusive-OR gates, wherein the 43 D flip flops (D0...D42) and the 16 Exclusive-OR gates are interleaved and connected in series sequentially; values obtained through xor between output signals (Q42...Q27) of higher 16-bit D flip flops (D42...D27) and 16-bit input signals form a 16-bit parallel descrambling sequence. The 16-bit parallel self-synchronous scrambler and descrambler have the advantages that the circuits are simple, serial data are changed into parallel data, furthermore, the working frequency is reduced greatly, the system reliability is improved, and realization of integrated circuit technique is facilitated.

Description

technical field [0001] The invention relates to the technical field of data communication, in particular to a 16-bit parallel self-synchronous scrambling / descrambling coder for transmitting GFP data frames. Background technique [0002] The General Framing Procedure (GFP for short) G.7041 / Y1303 specifies a general method for encapsulating user data into bit-synchronous or byte-synchronous physical transmission networks (such as SDH system: Synchronous Digital Hierarchy, synchronous digital system). A serial self-synchronizing scrambler and descrambler is specified in the standard. The so-called self-synchronization means that in any initial state, as long as the descrambler can correctly receive the scrambling code sequence, the receiving end can obtain synchronization after a certain period of time and recover the correct original data. When there is an error in the received symbol, it can also restore synchronization in a very short time. The self-synchronizing scramble...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L1/00H04J3/06
Inventor 曹鹏飞陈伟峰张睿王东峰
Owner TOEC TECH
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