e1 framing controller with output delay can be precisely configured and its working method

Abstract

The invention discloses an E1 framing controller with the ability to precisely configure the output delay and a working method. The controller includes: a bus interface unit, which is used for connecting the internal unit of the E1 framing controller and the CPU or service processing unit in the external gateway device The interface between; FIFO and related control logic unit are used to store and buffer E1 payload data and start the E1 framer; the parameter configuration storage unit transmits the output signal to the E1 framer for transferring mode configuration information and signal Command information; transmit the output signal to FIFO and related control logic unit for controlling FIFO reading and output control; E1 framer is used for parallel-to-serial conversion of E1 payload data and output in frames. The invention improves the integration of the system, provides a unified data access interface, sets the jitter buffer delay parameters, time slot occupancy configuration table, and channel-associated signaling, and saves external memory and corresponding storage controller units.

Description

technical field [0001] The invention relates to an E1 framing controller capable of precisely configuring the output delay and a working method. Background technique [0002] Packet Switching Network (PSN) or Packet Transport Network (PTN) is a packet-oriented transport network that can support time-division multiplexing services (such as E1 / T1 / E3 / STM) through end-to-end pseudowire emulation (PWE3, refer to RFC3985 specification) -n etc.). The corresponding encapsulation protocol standards are unstructured SAToP (refer to RFC4553), structured CESoPSN (refer to RFC5086) and TDMoIP (refer to RFC5087). [0003] Due to the inherent network congestion of the packet transmission network, inconsistent network node loads, and routing changes, there are differences in packet arrival times (called delay jitter). For time-division multiplexing services, gateway devices must use jitter buffers to compensate packet time. delay difference. Received message data enters the jitter buffer...

AI Technical Summary

Problems solved by technology

However, in application scenarios that are sensitive to delay time and have low network delay jitter, there is no need to use a large-capacity external memory, and the use of external memory will increase the processor overhead and the uncertainty of running time to a certain extent. Will increase system cost, system size and probability of failure

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