Static Random Access Memory and Write Redundancy Improvement Method in Embedded SiGe Process

Abstract

A static random access memory in an embedded silicon germanium process, comprising: a silicon-based substrate; an NMOS device; a PMOS device, the gate of the PMOS device is arranged on the silicon-based substrate, and the source region and the drain region of the PMOS device are respectively arranged In the silicon-based substrate on both sides of the gate, embedded silicon germanium is arranged in the source region and the drain region; the pull-up transistor is a PMOS semiconductor, and the gate of the pull-up transistor is arranged on the silicon-based substrate. The source region and the drain region of the pull-up transistor are respectively arranged in the silicon base substrate on both sides of the gate. The present invention increases the compressive stress in the channel of the PMOS device by arranging embedded silicon germanium in the source region and the drain region of the PMOS device, thereby improving the hole mobility; There is no embedded silicon germanium in the drain region, so that the compressive stress of the pull-up transistor in the channel direction is reduced, the carrier mobility is reduced, and the equivalent resistance of the pull-up transistor is increased, thereby improving the static randomness. Memory write redundancy.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a static random access memory in an embedded silicon germanium process and a method for improving write redundancy. Background technique [0002] As an important product in semiconductor memory, Static Random Access Memory (SRAM) in the embedded silicon germanium process has been widely used in high-speed data exchange systems such as computers, communications, and multimedia. [0003] Generally, the layout of the SRAM in the embedded silicon germanium process below 90nm includes three levels of active regions, polysilicon gates, and contact holes, and control transistors are respectively formed on the layout areas, and the control transistors is an NMOS device; a pull down transistor (Pull Down MOS), the pull down transistor is an NMOS device; a pull up transistor (Pull Up MOS), the pull up transistor is a PMOS device. However, in the SRAM in the existing embedded silico...

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Problems solved by technology

However, in the SRAM in the existing embedded silicon germanium process, the equivalent resistance of the pull-up transistor is small, which in turn leads to a small write margin (Write Margin) of the SRAM

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