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Data output circuit of semiconductor apparatus

A semiconductor and data technology, applied to logic circuits using semiconductor devices, logic circuits using specific components, instruments, etc., can solve problems such as deterioration of asynchronous parameter characteristics, operational failure, and difficulty in selecting margins for designers

Active Publication Date: 2014-02-12
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0026] Since the GIO to PIN margin (hereinafter, referred to as "margin") shows a timing difference between the simulation and the actually implemented circuit, it is difficult for the designer to choose an appropriate margin
[0027] When a large margin is set for the stability of operation, the characteristics of asynchronous parameters such as address access time (tAA) deteriorate
When a small margin is set in order to improve the tAA characteristics, it will cause operational failure

Method used

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  • Data output circuit of semiconductor apparatus
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  • Data output circuit of semiconductor apparatus

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Embodiment Construction

[0038] Hereinafter, a data output circuit of a semiconductor device according to the present invention will be described through various embodiments with reference to the accompanying drawings.

[0039] figure 2 is a schematic block diagram illustrating the configuration of a data output circuit 100 of a semiconductor device according to an embodiment, and image 3 is description figure 2 The circuit diagram of the internal configuration of the first signal generation module 200 , the read data path module 20 and the control signal path module 400 shown in .

[0040] Such as figure 2 As shown in , the data output circuit 100 of a semiconductor device according to an embodiment includes a first signal generation module 200 , a read data path module 20 , a control signal path module 400 , a delay time control module 500 and a second signal generation module 600 .

[0041] Such as image 3 As shown, the first signal generating module 200 includes a plurality of delayers DL...

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Abstract

The invention discloses a data output circuit of semiconductor apparatus. a data output circuit of a semiconductor device includes: a pattern data generation unit configured to generate pattern data in response to a bank selection signal, a variable delay unit configured to delay a source signal, which is generated in response to the bank selection signal, by a delay time corresponding to a delay control signal, a pattern control signal generation unit configured to generate a pattern control signal in response to an output signal of the variable delay unit, and a delay time control block configured to generate the delay control signal in response to the phases of the pattern control signal and the pattern data.

Description

[0001] Cross References to Related Applications [0002] This application claims priority from Korean Patent Application No. 10-2012-0086071 filed with the Korean Intellectual Property Office on Aug. 7, 2012, the entire contents of which are hereby incorporated by reference. technical field [0003] The present invention generally relates to a semiconductor device, and more specifically relates to a data output circuit of the semiconductor device. Background technique [0004] After receiving a read command, a semiconductor device (eg, a semiconductor memory device) transfers data stored in a corresponding memory cell to a pipe latch via a path (such as a global line GIO, etc.). [0005] The pipe latch receives and arranges the transmitted data in response to the control signal PINB, thereby generating output data. [0006] A predetermined timing margin should be guaranteed between the transmitted data and the input control signal to achieve stable data output. [0007] f...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K19/08
CPCG11C7/1066G11C29/022G11C7/222G11C29/023G11C7/22G11C7/1039G11C7/10
Inventor 金载镒
Owner SK HYNIX INC
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