Integrated circuit clock grid drive optimization method based on drive windows

Abstract

The invention discloses an integrated circuit clock grid drive optimization method based on drive windows. The method is implemented in the following steps: a clock grid is divided into the multiple drive windows according to the range of influence of each driver on the basis of low-pass filtering characteristics; the drive windows are traversed; the magnitude of load capacitance in the current drive window is estimated according to the current drive window which is traversed each time; according to typical input signal hopping time and the magnitude of the load capacitance in the current process, bilinear interpolation table lookup is conducted in a traversing mode to calculate device delay and output signal hopping time of all alternative drivers; the maximum hopping time and the maximum device delay not higher than values specified by a user are sequentially selected, a unit with the smallest area within a range specified by the user is used as the driver of the current drive window, and then clock grid drive optimization is completed. By means of the integrated circuit clock grid drive optimization method based on the drive windows, the effect that no drive surplus is caused under the condition of guaranteeing that the grid is driven reasonably can be achieved, the area occupied by a chip is reduced, the expandability is high, and the method can be conveniently combined with other grid optimization strategies.

Description

technical field [0001] The present invention relates to the field of integrated circuit (Integrated Circuit, hereinafter referred to as IC) design automation field of microelectronics technology, in particular to an integrated circuit clock grid driving optimization method based on a driving window. Background technique [0002] In the physical design of semi-custom integrated circuits, devices are basically selected from the cell library provided by the process manufacturer, so the timing and physical indicators of the cells need to be specially considered to meet various design requirements. The timing of the device mainly refers to the device delay and the output signal transition time, and the physical index of the device mainly concerns the size of the unit area. [0003] The device delay indicates the time elapsed when a signal passes through a logic gate. Generally, the time required for a 50% change in the input signal voltage to a 50% change in the output signal vol...

AI Technical Summary

Problems solved by technology

In today's large-scale chip design, there are often a series of negative effects such as wiring congestion caused by driver unit congestion, difficulty in timing convergence, excessive local voltage drop, and excessive local power consumption density. Inappropriate choice of type is also an important reason

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