18results about How to "Reduce area occupation" patented technology

The embodiment of the invention discloses a bus timeout monitoring method, device and system based on an AXI protocol, which are applied to the bus timeout monitoring system and comprise at least one AXI host and at least one AXI slave, a plurality of communication channels sharing a watchdog counter are arranged between the AXI host and the AXI slave, and the AXI host and the AXI slave share the watchdog counter. The method comprises the following steps: initiating an access request to a target AXI slave through a target communication channel, and recording request information associated with the access request to a register array in the target communication channel; obtaining a timeout time point corresponding to the access request; if response information of the target AXI slave is not received when the value of the watchdog counter reaches the timeout time point, determining that the access request is timeout; and triggering interruption, and reporting request timeout according to the information recorded by the register array. According to the technical scheme provided by the embodiment of the invention, the overtime problem in AXI transmission can be solved, and the accuracy and the real-time performance of overtime detection are ensured.

The invention relates to the technical field of high-performance computer networks, and discloses a high-performance on-chip cross network structure, which comprises a router group and a small cross line group, the router group comprises an input-stage router, an output-stage router and an intermediate-stage router; the small cross line group comprises cross lines between at least two stages of routers and is used for connecting the routers at all stages; the middle-level router comprises input ports and output ports, the number of the input ports and the number of the output ports are both smaller than or equal to a first threshold value, and the input ports of the middle-level router are connected with the routers of the corresponding number in the upper-level router; each output port of the middle-level router is respectively connected with a corresponding number of routers in the next-level router; the high-performance on-chip cross network structure has at least one connecting line for any pair of input-stage routers and output-stage routers. According to the invention, the problems of overlarge chip area occupation and performance reduction of a cross network structure can be solved.

The invention relates to a five-transistor half adder circuit, a digital memory computing array and a static random access memory, and the five-transistor half adder circuit comprises a first NMOS transistor N1, a second NMOS transistor N2, a first PMOS transistor P1, a second PMOS transistor P2 and a third PMOS transistor P3; the source electrode of the first NMOS transistor N1 is connected with the drain electrode of the first PMOS transistor P1 and the drain electrode of the second PMOS transistor P2 to form a first node SUM, the grid electrode of the first NMOS transistor N1 is connected with a voltage source, and the drain electrode of the first NMOS transistor N1 is grounded; the grid electrode of the second NMOS tube N2 and the grid electrode of the third PMOS tube P3 are connected to form a second node D; the source electrode of the first PMOS tube P1 and the grid electrode of the second PMOS tube P2 are connected with the second node D; the drain electrode of the third PMOS tube P3 and the drain electrode of the second NMOS tube N2 are connected to form a third node CO, and the source electrode of the third PMOS tube P3 is grounded; and the source electrode of the second NMOS tube N2 is connected with the grid electrode of the first PMOS tube P1 and the source electrode of the second PMOS tube P2 to form a fourth node C. The problem that an existing half adder circuit is complex in structure is solved.

The invention discloses a low-voltage ESD protection device and a manufacturing method thereof. The device comprises an N-type single crystal material layer, N+ polycrystalline silicon, an N-type base region, and a P-type base region. A first isolation medium layer, a first metal layer, a second isolation medium layer, and a second metal layer are sequentially arranged on the N-type single crystal material layer. The N+ polycrystalline silicon, the N-type base region, and the P-type base region are all arranged on the top of the N-type single crystal material layer. A P+ source region and an N+ source region are arranged in the N+ polycrystalline silicon. A thermal oxidation layer is arranged between the outside of the N+ polycrystalline silicon and the N-type single crystal material layer. A P+ source region is arranged in the N-type base region. A P+ source region, an N+ source region, an N+ source region, and a P+ source region are sequentially arranged in the P-type base region. The invention effectively improves the utilization rate of a chip and reduces the chip cost; does not increase the cell size, reduces the chip area occupied by maintaining the metal spacing, can reduce the cell size by about 20%, and improves the current discharge capacity by at least 50%.

The embodiment of the invention discloses a memory device, a control method thereof and a memory system, and the memory device comprises a memory array which comprises a plurality of memory planes; the peripheral circuit is coupled with the plurality of storage surfaces and comprises a plurality of first micro control units (MCUs) which are coupled with the plurality of storage surfaces in a one-to-one correspondence manner; and a cache coupled to each of the plurality of first MCUs, wherein each first MCU in the plurality of first MCUs is configured to respond to an operation control signal, acquire an operation parameter from the cache according to a preset access rule, and execute an operation on the storage surface correspondingly coupled with the first MCU according to the operation parameter.

This utility model discloses a folding cabinet door mechanism for narrow compartments, comprising a first cabinet door, a second cabinet door, a first door lock, a second door lock, a hinge, a guide rail, a slider, a lower cabinet door fixing bracket, an upper cabinet door fixing bracket, a guide rail fixing bracket, a rotating shaft, an upper rotating pin, and a lower rotating pin. The first and second cabinet doors are hinged together. The first and second door locks are respectively mounted on the first and second cabinet doors. The upper and lower rotating pins are located at the upper and lower ends, respectively, and are rotatably connected to the upper and lower cabinet door fixing brackets. The guide rail fixing bracket is fixed to the upper end of the opposite side of the compartment opening, and both ends of the guide rail are connected to the upper cabinet door fixing bracket and the guide rail fixing bracket, respectively. The slider slides within the guide rail. The lower end of the rotating shaft is connected to the second cabinet door, and the upper end of the rotating shaft is rotatably connected to the slider. This utility model has a simple structure, few parts, and low cost.

The invention provides a BCD device and a preparation method thereof, the BCD device comprises a substrate, an epitaxial layer, a super junction VDMOS unit and a plurality of planar transistor units, the epitaxial layer is located on a first surface of the substrate, the epitaxial layer is internally provided with a first region and at least one second region, and the second region is internally provided with at least one first medium voltage well; the super-junction VDMOS unit comprises at least two second medium-voltage traps and a back metal layer, the second medium-voltage traps are transversely arranged in the first region at intervals, and the back metal layer is located on the second surface of the substrate and electrically connected with the substrate; part of composition structures of the planar transistor units are located in the first medium-voltage traps in the corresponding second regions. The super-junction VDMOS unit is integrated in the BCD device, compared with a conventional LDMOS unit, the super-junction VDMOS unit has better current capacity, smaller area occupation and higher reliability, the performance and reliability of the BCD device are improved, the first medium-voltage well and the second medium-voltage well are prepared synchronously, and the BCD device has the advantages of being simple in manufacturing method, low in cost, high in reliability and the like.

The utility model discloses a lamp panel of a high-power deep ultraviolet LED sterilizing lamp. The lamp panel comprises a heat dissipation substrate, the deep ultraviolet LED chips are fixedly arranged on the heat dissipation substrate in a preset arrangement mode; wherein the irradiation taper angle theta of the deep ultraviolet LED chips is equal to 450, the chip spacing D of the adjacent deep ultraviolet LED chips is # imgabs0 #, and L'is the distance with obvious luminous power collapse. The high-power deep ultraviolet LED sterilizing lamp panel has the advantages of high efficiency, high power and low power consumption, is suitable for small-sized sterilizing lamps, occupies very small area of the whole circuit, and is very suitable for places such as stations, schools, hotels, hospitals and the like. In addition, a disinfection blind area can be avoided, and a more perfect disinfection effect is achieved.

The invention provides a display panel and a display device. The problem that in the prior art, the frame size of a display panel is large is solved. The display panel is provided with a display area and a frame area at least partially surrounding the display area, the frame area comprises a first frame area, an arc angle frame area and a second frame area which are connected in sequence, and the display panel comprises a first gate drive circuit located in the frame area; the first gate drive circuit comprises a plurality of first gate drive units, and the distance between every two adjacent first gate drive units in the second frame area and the arc angle frame area is larger than the distance between every two adjacent first gate drive units in the arc angle frame area.

The application relates to the technical field of low-power consumption of integrated circuits, and discloses a RAM (Random Access Memory) voltage maintaining circuit and method in a sleep mode, which comprises a reference current generating module, a current mirror array module, a core voltage generating module and a digital calibration control module; the reference current generating module generates nanampere reference current; the current mirror array module outputs programmable mirror current; the core voltage generating module converts the mirror current into output voltage VOUT; and the digital calibration control module compares Vto with Vref when the chip is working, and outputs a calibration signal to adjust the mirror current. The core voltage generating module comprises a PVT self-adaptive bias structure composed of NMOS and PMOS tubes, so that the output voltage is automatically adjusted according to process, voltage and temperature. The application adopts an intermittent working mode of "calibration during working and maintaining during sleeping", and combines an open-loop source follower architecture, so that typical static power consumption of 50nA, PVT self-adaptive adjustment, rapid awakening and extremely small chip area are realized, and the application can be widely applied to super-low-power-consumption devices such as the Internet of Things.

The utility model provides a material butt joint device which comprises a base (1), a first sliding rail (11), a second sliding rail (12) and a material butt joint device. The middle frame (2) is in sliding connection with the first sliding rail (11), and a second sliding rail (21) and a driving assembly (4) are arranged on the middle frame (2); the bearing platform (3) is in sliding connection with the second sliding rail (21) and is used for bearing materials; the driving assembly (4) drives the middle frame (2) through a first transmission assembly (5) and drives the bearing platform (3) through a second transmission assembly (6) so as to drive the middle frame (2) and the bearing platform (3) to move in the same direction relative to the base (1). According to the technical scheme provided by the embodiment of the utility model, the occupied area of the material butting device in the gene detection equipment is saved, and the integration level of the gene detection equipment is improved.

The invention relates to the technical field of integrated circuits, and provides an impedance matching circuit and method of a single-branch RRAM resistance network, and the impedance matching circuit of the single-branch RRAM resistance network comprises a positive electrode impedance calibration module, a negative electrode impedance calibration module, a user impedance calibration module and a DCI adjustment module. Each of the positive impedance calibration module, the negative impedance calibration module and the user impedance calibration module comprises an RRAM (Resistance Random Access Memory) resistance network structure; the anode impedance calibration module comprises an accurate matching resistor, a switching tube, a post-stage comparator and the RRAM resistor network structure; the cathode impedance calibration module comprises an accurate matching resistor, a switching tube, a post-stage comparator and the RRAM resistor network structure; the user impedance calibration module comprises a switch tube and an RRAM resistance network structure. According to the invention, the impedance matching resistor network is subjected to circuit simplification, the chip area occupation is reduced, and the circuit power consumption is saved.

This invention discloses a high-bandwidth, notch-free hybrid magnetocurrent sensor circuit, comprising a low-frequency path, a high-frequency path, a differential amplifier, a compensation path, and a dual-to-single converter. The low-frequency path utilizes a Hall effect sensor and auxiliary bias circuitry to detect the low-frequency component of the current, and simultaneously suppresses sensitivity drift and common-mode drift by replicating a negative temperature coefficient voltage. In the high-frequency path, the integrator consists of two paths with the same gain-bandwidth product but different low-frequency gains, and gain flatness is improved through compensation technology. The servo loop employs active capacitor amplification technology, using small-area resistors and capacitors to achieve ultra-low-frequency poles. The outputs of the high- and low-frequency paths are combined via a differential amplifier and then pass through a subtractor and a high-pass filter to form a compensation path for eliminating chopper ripple. Finally, the signals are converged in the dual-to-single converter to obtain a notch-free broadband output. This invention simultaneously solves problems such as chopper notch, gain unevenness caused by pole-zero mismatch, and the use of large-area passive components.

The utility model relates to a three-axis micro-electro-mechanical gyroscope and a micro-electro-mechanical gyroscope. A microelectromechanical gyroscope includes a die of semiconductor material forming a substrate and a detection structure suspended over the substrate. The detection structure has a main extension in a horizontal plane, is symmetric with respect to the central symmetry axis, and is provided for each gyroscope detection axis with: a first pair of detection masses arranged on a first side of the central symmetry axis; and a second pair of proof masses arranged on a second side of the central symmetry axis, the second side being opposite to the first side in the horizontal plane. The proof masses in each pair are capacitively coupled to a respective stator electrode according to a differential detection scheme. The stator electrodes are symmetrically arranged on opposite sides of the central symmetry axis with respect to each other.

The utility model relates to the technical field of fiber manufacturing, in particular to a ceramic yarn guide for two sides of a chemical fiber spinning interlacer, which adopts the technical scheme that the ceramic yarn guide comprises a main yarn guide, an insertion plate, a mounting groove and an insertion groove, and an additional yarn guide is fixedly mounted at the rear end of the main yarn guide through a connecting seat; the mounting groove is formed in the front end of the connecting seat; wherein the connecting seat is glued to the rear end of the main yarn guider through the mounting groove; the inserting groove is formed in the rear end of the connecting seat; the plug board is arranged at the front end of the additional yarn guide; wherein the size of the plug board is matched with that of the plug groove; wherein the front end of the additional yarn guide is inserted into the inserting groove through the inserting plate. The spinning winder solves the problem that when the number of the yarn guide holes needs to be increased, the area of the two sides of the spinning winder is limited, and the number of the increased yarn guide holes is limited.

The present invention provides a test circuit for E-fuse fusing characteristics, comprising a switch controller, a voltage source, at least one E-fuse to be tested and a switch module; the output end of the switch control module is connected to the switch module; one end of the E-fuse to be tested is connected to a fixed potential end, and the other end is connected to the voltage source, and each E-fuse to be tested is connected to a switch module for controlling the on-off of a test circuit where the E-fuse to be tested is located through the switch module; the test circuit greatly increases the number of testable DUTs, saves the area of ​​a test chip, and adopts a fusing voltage and a non-fusing voltage for testing, so as to judge whether the fusing of the E-fuse is caused by the test; when a pulse voltage test signal is adopted, it not only avoids the hidden danger of current accumulation caused by testing the E-fuse in a traditional addressable test structure, but also can further reduce the area occupied by the peripheral test circuit.

The invention discloses a switchable wired keyboard and a system thereof, and relates to the technical field of keyboard control. The switchable wired keyboard comprises a keyboard body, a main control module, a switching module and a plurality of expansion interfaces, the switching module is arranged in the keyboard body and electrically connected with the main control module and the expansion interfaces, and the switching module is used for switching off the connection of the first terminal and switching on the connection of the second terminal according to a switching signal output by the main control module; the plurality of expansion interfaces are arranged on one side of the width direction of the keyboard body and are used for establishing communication connection with connecting equipment and supplying power to the connecting equipment; wherein the plurality of expansion interfaces comprise a plurality of input interfaces which are used for receiving output signals of the terminal; and the plurality of output interfaces are used for outputting the output signals acquired by the input interfaces to input equipment. The invention aims to improve the comprehensive performance of the keyboard.

The utility model discloses a rubber open mill which comprises a driving motor and a reduction gearbox, the reduction gearbox comprises two input shafts and two output shafts, and the driving motor is in transmission connection with one input shaft through a coupler; the main machine comprises a machine frame, a first roller and a second roller, the first roller and the second roller are rotationally arranged on the machine frame, the first roller and the second roller are arranged at an interval and are in transmission connection through a speed ratio gear, and pull rope emergency stop devices are arranged on the two sides of the top of the machine frame; the number of the main machines is two, and each output shaft of the reduction gearbox is in transmission connection with the first roller in one main machine through a gear coupling. According to the rubber open mill disclosed by the utility model, the reduction gearbox is updated, so that the first rollers in the two main machines are driven by the single driving motor to operate simultaneously, and the rubber open mill has different working modes to correspond to different capacities and does not need to be moved; due to the structure of the driving motor and the reduction gearbox, the occupied space of the rubber open mill is also reduced, and the production cost is reduced.