Memory circuit and method for reading data by applying same

Abstract

The invention provides a memory circuit and a method for reading data by applying the same. The memory circuit comprises a control circuit and a global memory array which are connected with each other, wherein the global memory array comprises a global amplifying circuit, at least a segment memory array, segment amplifying circuits and segment gating circuits, wherein the segment amplifying circuits and the segment gating circuits are connected with the segment memory arrays; each segment memory array comprises at least a group memory array, group amplifying circuits and group gating circuits, wherein the group amplifying circuits and the group gating circuits are connected with the group memory arrays; and the control circuit comprises a read/write control unit and an ECC (error correcting code) circuit. The memory circuit and the method have the following advantage: the area can be reduced as far as possible on the basis of realizing the functions of a static memory circuit.

Description

technical field [0001] The invention relates to the technical field of memory, in particular to a memory circuit and a method for reading data using the memory circuit. Background technique [0002] Static RAM memory blocks based on conventional six-transistor (6T) memory cells have been a powerful tool for development in many embedded designs because this memory structure fits well into mainstream CMOS process flows without adding any additional process steps. [0003] In general, basic interleaved coupled latches and active load cells make up a 6T memory cell, which can be used in memory arrays ranging in size from a few bits to several megabits. Carefully designed such memory arrays can meet many different performance requirements, depending on whether the designer chooses a CMOS process optimized for high performance or low power. The access time of an SRAM block produced by a high-performance process can easily be lower than 5ns in a 130nm process, while the access tim...

AI Technical Summary

Problems solved by technology

[0006] However, the six transistors used to make up the latches and high-performance loads result in a large 6T cell size, which greatly limits the storage capacity that can be realized in memory arrays

The main reason for this limitation is the area consumed by the memory block and the cell leakage due to the technology process node used to implement the chip design

As the ratio of the total area of ​​the memory array to the total chip area increases, so does the chip size and cost

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