16 results about "Group memory" patented technology

The invention relates to the technical field of artificial intelligence and multi-agent cooperative control, in particular to an agent autonomous cooperation method and system based on group hierarchical cooperation, and the method comprises the steps: responding to a natural language task request input by a user; generating a preliminary task execution plan based on the task description data, selecting expert agents matched with sub-tasks in the task execution plan from the group, and generating a task allocation instruction to perform task cooperation; and each expert agent receives the task allocation instruction to execute the corresponding sub-task, writes an execution state, a stage result and intermediate data into a group memory space in real time in an execution process, and performs semantic integration and induction after all the sub-tasks are executed to generate a unified task output result. Under the unified command of the super agent, each expert agent can realize autonomous cooperation and real-time information sharing based on the group memory space, and realize adaptive dynamic re-planning when the task is abnormal or the environment is changed.

The application provides a non-associated grouping memory failure unit analysis method, first, the position information of all memory failure units is obtained through a chip tester to form a fault bit map; then, based on the position information characteristics in the fault bit map, all the failure units in the fault bit map are grouped based on a grouping principle to form a multi-failure group and a single-failure group; then, based on the repair principle of the memory failure unit, the failure units in each group are analyzed for repair to determine whether the failure units of the memory chip can be repaired; if the failure units of the memory chip can be repaired, a repair solution is given. The application divides all the failure units of the memory chip into independent multi-failure groups and single-failure groups based on the non-associated grouping memory failure unit analysis method, and then analyzes and finds the redundancy repair solution of each failure group, which can more reasonably allocate the redundancy resources and effectively improve the repair efficiency of the memory failure units.

A volatile memory device comprising: a first chip comprising a sub word line drive (SWD) circuit that applies a word line enable voltage to activate one or more selected memory cells; and a second chip bonded to the first chip such that a surface of the first chip and a surface of the second chip are in contact with each other, the second chip comprising a first memory cell, a second memory cell, a first conductive line connecting the first memory cell to the SWD circuit, and a second conductive line connecting the second memory cell to the SWD circuit, wherein the first memory cell receives the first word line enable voltage, and wherein the second memory cell receives the second word line enable voltage.

The present application belongs to the technical field of computers. Disclosed are a cache management method and apparatus. The method is applied to a cache of a computer system, and the computer system further comprises a processor in communication with the cache. The method comprises: grouping memory access requests from a processor; applying different allocate policies to two groups of memory access requests; comparing performance costs consumed by processing the two groups of memory access requests after the corresponding allocate policies are applied to the two groups of memory access requests; and on this basis, determining a target allocate policy for the remaining groups of memory access requests other than the two groups of memory access requests. By means of the method, a better allocate policy can be determined for the remaining groups of memory access requests, and the better allocate policy can achieve caching of data that is highly likely to be accessed again by the processor in the future, thereby improving subsequent cache hit rates of memory access requests in the remaining groups, that is, improving the performance of the processor.

A method of determining log likelihood ratios (LLRs) for soft decoding based on information obtained from hard decoding in a storage system configured to perform hard decoding and soft decoding of a low density parity check (LDPC) codeword is provided. The method includes performing hard decoding of the codeword in a page, the hard decoding including a first hard read using a predetermined hard read threshold voltage and one or more re-reads, and grouping memory cells in the page into a plurality of bins based on read threshold voltages used for the first hard read and the one or more re-reads. The method also includes calculating parity sums and counts of ones for the memory cells in each bin, and determining the LLRs for the memory cells in each bin based on read data, the parity sums, and the counts of ones for each bin.

The present disclosure relates to techniques for enabling dynamic memory evolution in large language models (LLMs) by selectively integrating user-provided facts or information during real-time interactive sessions. The disclosed techniques may include, upon receiving an input prompt from a user, generating a set of memory-weighted tokens using multiple transformer layers, each coupled to a dedicated memory pool comprising memory tokens that represent the model's internal knowledge. These memory-weighted tokens may be analyzed to identify salient, new, or distinct information in the input prompt relative to the existing memory content. The identified knowledge may then be incorporated into one or more memory pools prior to generating a response. The disclosed techniques may enable the LLM to autonomously adapt and refine its internal memory based on user-provided domain knowledge, personal preferences, or factual corrections, facilitating progressive enhancement of internal knowledge without reliance on manual retraining or calibration.

The present application relates to a management method and management apparatus for a hybrid memory system, a device, and a medium. The method includes: acquiring a write hotness value and an access hotness value of a currently accessed memory page; comparing the write hotness value with a specified write hotness threshold, generating write hotness page migration flag information; comparing the access hotness value with a specified access hotness threshold, generating access hotness page migration flag information; grouping a hybrid memory, generating memory page management information corresponding to the hybrid memory based on memory page information of all grouped memory banks; determining whether the currently accessed memory page is a hot data page based on the write hotness page migration flag information, the access hotness page migration flag information, and current memory page management information, performing data migration based on a preset cold and hot data page migration strategy.

The invention discloses an intelligent response method and device based on memory system driving, equipment and a medium. The method comprises the following steps: in response to an input query statement, coding the query statement into a situation vector in combination with current situation information; based on the context vector, retrieving a group of memory units related to the context vector in a dynamic memory knowledge graph in multiple dimensions; based on a preset memory association analysis rule, constructing an association relationship between a group of memory units to obtain a memory sub-graph; and based on the memory sub-graph, performing multi-modal fusion on the memory fragments corresponding to the group of memory units to generate a natural language response. Through the mode, the memory can be represented as the memory unit and stored in the dynamic memory knowledge graph, so that the memory ability of the intelligent agent is greatly enhanced; according to the method, multi-dimensional retrieval is carried out in the dynamic knowledge graph, the most relevant memory unit is quickly and accurately retrieved, and accurate and coherent natural language response is generated through multi-modal fusion, so that the response efficiency and the response quality are improved.

The application relates to an in-memory logic computing system of one or non-logic type, which comprises a timing control unit D, at least one set of memory diodes A, B and C and at least one control unit U; the negative poles of the five memory diodes are connected to one end of a bit line, the positive poles of the five memory diodes are connected to different word lines, the other end of the bit line is connected to the control unit U, and the control unit U is used for controlling the bit line to be grounded or pulling the voltage on the bit line to -1 / 2VDD. The in-memory logic computing can be realized in a large-scale storage array, the in-memory computing of the non-Von Neumann architecture is popularized to the general computing field, the energy efficiency and speed of the in-memory computing chip are improved, and the in-memory computing chip is applied to the logic operation field.

The invention relates to the technical field of memory management, in particular to a terminal group memory sharing management system which comprises a computing power intensity identification module, a quota granularity control module, an intention priority module, an access arbitration sorting module and a cold region recognition and recovery module. According to the method, the performance level is formed by performing quantitative mapping on the task processing efficiency and the execution delay of the terminal in the specific time window, the quota upper limit is calculated according to the performance level and the system load, the page block granularity parameter is set, the memory page resource configuration of each terminal is dynamically adjusted, and the pre-behavior vector is constructed in combination with the historical access behavior. Extracting a plurality of data items reflecting the access intention to generate a priority control quantity, sorting the access requests in a descending manner, executing memory page access according to mapping parameters, identifying an access cold area according to an access period offset, and executing address remapping; and the resource dynamic adaptation capability is guaranteed, the access sorting precision is improved, and the invalid occupation and conflict rate is reduced.

A memory processing unit (MPU) can include a first memory including a plurality of memory regions and a plurality of processing regions. One or more of the plurality of memory regions can be configured in a corresponding pluralities of memory blocks. The memory blocks can be configured to store weights in a selected one of a plurality of bit precisions. The plurality of processing regions can be interleaved between the plurality of regions of the first memory. The processing regions can include a plurality of core groups, wherein the core groups include one or more compute cores.

This application discloses a memory management method, apparatus, electronic device, and storage medium. The memory management method includes: grouping memory pages corresponding to different processes of a target application currently running on the electronic device to obtain multiple memory groups, wherein the target process information of the processes corresponding to memory pages in the same memory group is matched; if it is determined that a first memory page corresponding to a first process of the target application needs to be swapped out, then the first memory page is swapped out to the target storage area corresponding to the target memory group where the first memory page is located. This method can improve the flexibility of memory management.

The invention discloses a memory data management method and device, electronic equipment and a storage medium. The method comprises the following steps: acquiring device memory data corresponding to each device in the same environment, wherein the device memory data comprises at least one piece of device use information and / or personal information of at least one member; determining a relation group memory tag and at least one member memory tag according to the device memory data of all devices in the environment; the memory data is constructed according to the group memory tag and the member memory tag, and the memory data is multi-level structured data, so that the problem of data management disorder caused by memory data redundancy and non-uniform formats is avoided; scattered memory data is converted into an effective basis of an equipment regulation and control strategy which can directly support and output adaptive group generality and meet individual health requirements, and the difficulty in understanding and calling the memory data by the artificial intelligence equipment is effectively reduced.

A volatile memory device includes: a first chip comprising a sub word line driving (SWD) circuit that applies a word line enable voltage to activate one or more selected memory cells; and a second chip bonded to the first chip so that a surface of the first chip and a surface of the second chip are in contact with each other, the second chip comprising a first memory cell, a second memory cell, a first conductive line connecting the first memory cell to the SWD circuit, and a second conductive line connecting the second memory cell to the SWD circuit, in which the first memory cell receives a first word line enable voltage, and in which the second memory cell receives a second word line enable voltage.

A memory system and a method of controlling the same. An embodiment disclosed herein relates to a memory device including a set of memory cells and a memory controller. In one aspect, each of the set of memory cells includes a select transistor and a storage component connected in series between a corresponding bit line and a corresponding source line. In one aspect, the memory controller is to: apply a first write voltage to a bit line coupled to a selected memory cell; apply a second write voltage to a word line coupled to a gate electrode of a select transistor of the selected memory cell during a first time period; and apply a third write voltage to a source line coupled to the selected memory cell. The second write voltage can be between the first write voltage and the third write voltage.

The invention discloses a system and an operation method of a three-dimensional accelerator and a multiplication and accumulation device. In one aspect, a system includes a plurality of memory layers, each including a group of memory groups. The system may include a multiply-accumulate layer including a multiply-accumulate array having a plurality of multiply-accumulate devices. Each of the multiply-accumulate devices may be coupled to a respective memory group of the group of memory groups through at least one via structure. The group of memories and the multiply-accumulate devices can be respectively configured in a predetermined number of rows and columns.