Memory circuit and method for reading data by applying same

Abstract

The invention provides methods for reading and writing-in data by applying a memory circuit. The memory circuit comprises a control circuit with an ECC (error correcting code) circuit and a multistage segmented global memory array. The global memory array is divided into group memory arrays and segment memory arrays; the segment memory arrays comprise the group memory arrays and group amplifying and gating circuits; the global memory array comprises the segment memory arrays, segment amplifying and gating circuits and a global amplifying circuit; the global amplifying circuit is connected with the segment amplifying and gating circuits by a global bit line; the segment amplifying and gating circuits are connected with the group amplifying and gating circuits by segment bit lines; the group amplifying and gating circuits are connected with memory units in the group memory arrays by group bit lines; and the area of a memory can be effectively reduced through the multistage segmented method. The control circuit with the ECC circuit is used for checking and correcting the data after reading the data and before writing-in the data, therefore the data read / write accuracy can be ensured,and the chip yield can be effectively improved.

Description

technical field [0001] The invention relates to the technical field of memory, in particular to a memory circuit and a method for reading data using the memory circuit. Background technique [0002] Static RAM memory blocks based on conventional six-transistor (6T) memory cells have been a powerful tool for development in many embedded designs because this memory structure fits well into mainstream CMOS process flows without adding any additional process steps. [0003] In general, basic interleaved coupled latches and active load cells make up a 6T memory cell, which can be used in memory arrays ranging in size from a few bits to several megabits. Carefully designed such memory arrays can meet many different performance requirements, depending on whether the designer chooses a CMOS process optimized for high performance or low power. The access time of an SRAM block produced by a high-performance process can easily be lower than 5ns in a 130nm process, while the access tim...

AI Technical Summary

Problems solved by technology

However, because the yield rate of the existing memory circuit itself is difficult to guarantee, it is very easy to cause errors in the data reading and writing process

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