Dual Instruction Multiple Floating Point Operand Division Controller

Abstract

A dual-instruction multi-floating-point operand division operation controller includes a dual-port read-only-write-only memory, a command and its multi-operand write timing control module, a floating-point operand read timing control module, a memory data empty flag controller and Configure the operation and output control module; the controller uses FPGA to design a hard-wired control circuit, which can store two instructions, and the two instructions can be processed in parallel, one instruction is executed, and the other instruction is to be executed; or one instruction is executed, and the other instruction is written input; or an instruction operand is being written and read out at the same time; the write timing pulse generated inside the controller controls the continuous writing of multiple operands; the read timing pulse synchronized with the system Clock autonomously controls the operation of multiple floating-point numbers The division operation does not occupy the system bus. Executing one instruction is equivalent to executing multiple division instructions by the microprocessor, which reduces the number of operations for the system to fetch instructions, decode, transfer floating-point operands, and write back operation results.

Description

Technical field [0001] The invention relates to a dual-instruction multi-floating-point operand division operation controller, in particular to a dual-instruction multi-floating-point operand division operation control circuit and a timing control method based on hard-wired FPGA parallel operation circuits. Background technique [0002] The floating-point division arithmetic implements 2 32-bit floating-point division operations that comply with the IEEE754 standard; division operations are several times longer than addition / subtraction operations and multiplication operations. The system needs to output two floating-point operands in time before each operation , Or 1 floating point operand, the 2 operand input of the arithmetic unit requires 2 registers to ensure the stability of the dividend and divisor input during the division operation, and the microprocessor can be transferred during the division operation Process other programs, and read the operation result in time after ...

AI Technical Summary

Problems solved by technology

[0002] The floating-point number division operator realizes the division operation of two 32-bit floating-point numbers conforming to the IEEE754 standard; the division operation is several times longer than the addition / subtraction operation and multiplication operation, and the system needs to output 2 floating-point operands in time before each operation , or 1 floating-point operand, the 2 operand inputs of the arithmetic unit need 2 registers to ensure the stability of the dividend and divisor input during the division operation, and the microprocessor can transfer to Process other programs, and read the operation results in time-sharing after the operation is completed; for the continuous execution of the division operation of multiple operands, and the operation results are used as the dividend, the microprocessor needs to transmit the operand as the divisor and the operation as the dividend multiple times in time-sharing The operation of writing back the result; the design of the floating-point number division operator also adopts the method of pipeline execution, and the operation process is divided into several modules. The modules are executed sequentially, and the operation result of each instruction in the pipeline needs to be written back after the operation; but for the executed floating-point number division operation, the operation result of the previous operation instruction needs to be used as the dividend instruction, so the pipeline of the floating-point number division operation The operation loses its effect, which affects the execution speed of the floating-point number division operation instruction

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