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3D IC and 3D CIS structure

A technology of integrated circuits and sensors, applied in the field of 3D integrated circuits and 3D image sensor structures, can solve problems such as FET performance impact

Active Publication Date: 2014-03-26
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Unfortunately, these TSVs can be highly stressed, which will adversely affect the performance of the FETs in the CIS

Method used

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  • 3D IC and 3D CIS structure
  • 3D IC and 3D CIS structure
  • 3D IC and 3D CIS structure

Examples

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Embodiment Construction

[0041] The making and using of various preferred embodiments of the invention are discussed in detail below. The present invention, however, provides many applicable concepts that can be implemented in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

[0042] The invention will be described with reference to preferred embodiments in a specific context, namely a three-dimensional (3D) integrated circuit or a 3D complementary metal-oxide-semiconductor (CMOS) image sensor (CIS). However, the concepts in the present invention are also applicable to other integrated circuits or semiconductor devices.

[0043] now refer to figure 1 , an embodiment of integrated circuit 10 is shown. The integrated circuit 10 includes a first wafer 12 , a first back end of line layer 14 , a second wafer 16 and a second back end of line layer 18 . In an embodi...

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PUM

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Abstract

An embodiment integrated circuit includes a first device supporting a first back end of line layer, the first back end of line layer including a first alignment marker, and a second device including a spin-on glass via and supporting a second back end of line layer, the second back end of line layer including a second alignment marker, the spin-on glass via permitting the second alignment marker to be aligned with the first alignment marker using ultraviolet light. The invention also discloses a 3D IC and s 3D CIS structure.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, and more specifically, to 3D integrated circuits and 3D image sensor structures. Background technique [0002] Complementary metal oxide semiconductor (CMOS) image sensors (CIS) typically utilize a series of photodiodes formed in an array of pixel regions on a semiconductor substrate to sense when light is directed at the photodiodes. A transfer transistor such as a field effect transistor (FET) may be formed adjacent to each photodiode in each pixel region to transmit a signal generated according to light sensed within the photodiode for a required time. This enables the photodiode as well as the transfer transistor to capture an image at a desired time by operating the transfer transistor at a desired time. [0003] A conventional CIS can be formed in a front illuminated (FSI) configuration or a back illuminated (BSI) configuration. Regardless of the configuration in which it i...

Claims

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Application Information

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IPC IPC(8): H01L27/146H01L23/544H01L21/68
CPCH01L27/088H01L23/544H01L27/14618H01L2223/54426H01L21/6835H01L2221/68363H01L2221/6834H01L2221/68327H01L2924/0002H01L2924/00
Inventor 匡训冲
Owner TAIWAN SEMICON MFG CO LTD
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