A method and system for improving dynamic redundant multithreading performance and reducing power consumption overhead

Abstract

The invention discloses a method for reducing dynamic redundant multithreading performance and power consumption overhead, comprising the steps: an instruction decoding stage: reading an instruction operation code in the program operation process, recognizing an NOP instruction, and adding 1 to the statistic of the NOP instruction; an instruction emission stage: when reading a register, using a register number index record table to set a corresponding zone bit to be 0; an instruction submitting stage: using the register number index record table to look up the corresponding zone bit, wherein if the content is 1, the instruction for writing the register is a dynamic dead instruction, and 1 is added to the statistic of the dead instruction, and in the instruction submitting stage, the zone bit is set to be 1 no matter whether the content of the zone bit is 0 or 1. Every time the program operates a certain number of instructions, the dynamic dead instruction, NOP instruction statistical information and other crucial statistics are input into a constructed linear regression prediction model, and an AVF (Architectural Vulnerability Factor) of a processor component is predicted; when the AVF of the processor component is high, a redundant thread is started to improve the reliability; when the AVF of the processor component is low, the redundant thread is closed to improve the performance and reduce the power consumption.

Description

technical field [0001] The invention relates to the technical field of processor reliability, in particular to a method and system for reducing dynamic redundant multi-thread performance and power consumption overhead. Background technique [0002] In integrated circuits, ever-decreasing power supply voltages, higher and higher operating frequencies, ever-decreasing node capacitances, and rapidly increasing chip complexity make circuits more and more sensitive to environmental influences. High-energy particles (mainly from cosmic radiation, nuclear radiation, the atmosphere and packaging materials) bombard semiconductor devices, as well as noise and interference in the external environment, causing logic bits to flip and cause logic failures in integrated circuits. Since this kind of fault has the characteristics of transient, recoverable, random location and time, and will not cause permanent device failure, it is called soft error. As Moore's Law continues to be effective...

AI Technical Summary

Problems solved by technology

However, if you do not consider the impact of dynamic dead instructions, but only predict AVF based on the size and occupancy rate of processor components, it will lead to overestimation of AVF, open unnecessary redundant threads, and bring unnecessary performance and power consumption overhead.

Because the calculation of the occupancy rate of the processor unit does not remove the dynamic dead instructions that may reside in the processor unit (during program execution, the occurrence of soft errors in dynamic dead instructions will not affect the program execution result), thus overestimating the processing The effective occupancy rate of the processor unit, but the occupancy rate is a key characteristic for predicting the AVF of the processor unit. When the occupancy rate of the processor unit is high, its predicted AVF is likely to be high

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