A method of implementing soe in fpga-based soe system
A system implementation, IEEE1588 technology, applied in general control systems, control/regulation systems, time-division multiplexing systems, etc., can solve the problems of inflexible use and high cost, and achieve the effect of improving reliability
Active Publication Date: 2018-10-02
STATE NUCLEAR POWER AUTOMATION SYST ENGCO
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Problems solved by technology
In order to establish a high-precision IEEE1588 network time synchronization system, it is necessary to achieve high-precision time tag capture. The current time tag capture method has the problems of inflexibility and high cost. An economical, flexible, practical and efficient time tag is urgently needed. Tag capture method
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[0019] figure 1 It is a functional block diagram of the SOE system of the present invention. Such as figure 1 As shown, a SOE system based on FPGA, including CPU, PHY chip and FPGA, is characterized in that: FPGA is located between CPU and PHY chip, is connected with CPU and PHY chip respectively through MII interface; FPGA built-in IEEE1588 packet analysis module, SOE event monitoring module and free-running clock module.
[0020] Utilize above-mentioned SOE system to realize the method for SOE, it is characterized in that:
[0021] (1) System time synchronization, including the following steps:
[0022] a. The IEEE1588 data packet analysis module monitors the sending and receiving data packets between the CPU and the PHY chip. When the IEEE1588 data packet analysis module obtains the data packets, it records the current relative time information generated by the free timing clock module;
[0023] b. IEEE1588 packet parsing module parses the packet obtained, and when the ...
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The invention belongs to the field of a distributed control system of the field of industrial control, and discloses an FPGA-based SOE system and an SOE realization method thereof. The FPGA-based SOE system is characterized in that: an FPGA is arranged between a CPU and a PHY chip, and the FPGA is respectively connected with the CPU and the PHY chip via an MII interface; and an IEEE1588 data packet parsing module, an SOE event monitoring module and a free timing clock module are arranged in the FPGA. A high-precision IEEE1588 time synchronization system is quite flexibly realized with an FPGA+CPU framework, based on which the high-resolution SOE system is simply realized. Based on the FPGA technology, software is substituted by hardware so that reliability, anti-interference performance and flexibility of the system are enhanced. The system can select resources for meeting the required FPGA chip according to actual application, and a chip memory with appropriate size can also be flexibly developed according to the actual application.
Description
technical field [0001] The invention belongs to the field of distributed control systems in the field of industrial control, and in particular relates to an FPGA-based SOE system applied to input and output signals and a method for realizing SOE. Background technique [0002] With the rapid development of computer and network technology, the degree of intelligence of industrial control systems is getting higher and higher, the scale of the system is getting bigger and bigger, and the amount of information processed is getting bigger and bigger, which brings challenges to system event analysis and fault analysis. , how to record system events has become an important topic. In response, the control system puts forward SOE requirements. The full name of SOE is SequenceOf Event, which is generally translated as sequence of events. The SOE system can record the moment of signal change in the system and record the time of system event occurrence, which can be used for system eve...
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IPC IPC(8): G05B19/042H04J3/06
Inventor 王楠胡中泽赵宝平张晓印
Owner STATE NUCLEAR POWER AUTOMATION SYST ENGCO