Data processing method and device

Abstract

The invention discloses a data processing method and device. The method comprises the steps of generating a first address signal according to a first clock signal, and writing a first data signal in a memory address, corresponding to the first address signal, in a first memory area according to the first clock signal; if the phase difference, relative to a second clock signal, of the first clock signal is located in a first preset section, using the rising edge of the second clock signal for collecting the first address signal so as to generate a second address signal, and reading data from a memory address, corresponding to the second address signal, in the first memory area according to the second clock signal; if the phase difference is located in a second preset section, using the falling edge of the second clock signal for collecting the first address signal to generate a third address signal, and reading data from the memory address, corresponding to the third address signal, in the first memory area according to the second clock signal; using the read data as a second data signal. According to the data processing method and device, the problem caused by the insufficient timing sequence margin of a data clock domain crossing transmission path is solved.

Description

technical field

[0001] The present invention relates to the field of sequential logic circuits, in particular to a data processing method and device. Background technique

[0002] In the existing solutions for cross-clock domain transmission of data signals, the transition edge of one clock signal is usually used to collect the data signal corresponding to another clock signal, so as to obtain the data signal corresponding to the previous clock signal. However, in this scheme, the timing margin of the data signal on the transmission path transmitted across the clock domain is uncontrollable and uncertain, and its timing margin can be larger in one situation or larger in another. When the timing margin is small, because the duration of the updated value of the data signal as the acquisition object is relatively short, its data state is relatively unstable, so the collected data is not accurate, which affects the Reliability of transmission of data signals across clock domain...

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