Silicon carbide mosfet cell structure and method for forming silicon carbide mosfet cell structure

Abstract

In one embodiment, the present invention comprises a MOSFET containing independent MOSFET units, and each MOSFET unit comprises a U-shaped trap (228) (P-type) and two parallel sources (260) (N-type) formed in the trap; a plurality of source crosspieces (262) (N-doped) are connected with the sources (260) at a plurality of positions, and a region between two crosspieces (262) comprises a body (252) (P-type). The characteristics are formed on an N-type epitaxial layer (220), and the N-type epitaxial layer (220) is formed on an N-type substrate (216). A contact (290) extends, spans and is contacted with the plurality of source crosspieces (262) and the bodies (252), and the legs of a first trap and a second adjacent trap are covered with a grid oxide and a grid contact to respond to a grid voltage to reverse a conductivity type. The MOSFET comprises the plurality of units to obtain an expected low-channel resistance, and unit regions are formed by utilizing a self-alignment technology and by some states during a manufacture process.

Description

technical field [0001] Embodiments presented herein relate generally to silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET) cell structures and methods for forming SiC MOSFETs. Background technique [0002] In a conventional lateral MOSFET, current flows horizontally from source to drain along a narrow channel doped with material of the second conductivity type (both the source and drain regions are doped with material of the first conductivity type). A voltage applied to the gate contact overlying the channel inverts the conductivity type of the channel allowing majority carriers to flow from source to drain. Because the channel is narrow, conventional MOSFETS have small drain currents and correspondingly low power ratings. [0003] Power (high current) MOSFETS use many different device geometries to increase the maximum current and power rating of the device. These devices have current ratings from about 1A to 200A and power ratings from abou...

AI Technical Summary

Problems solved by technology

However, there is a need for continued improvement, especially as feature sizes shrink and alignment tolerances become more difficult to meet

But self-alignment technology provides precise and repeatable device structures and thus increases device yield

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