Comparative method of layout and schematic uniformity of multi-power-domain system with black box IPs

Abstract

The invention discloses a comparative method of layout and schematic uniformity of a multi-power-domain system with black box IPs. The method is achieved mainly by modifying a layout netlist and a schematic netlist, and all the modifications are achieved by modifying and executing script files. The method comprises the steps of finding out the names of all power ports of all function modules of a chip, analyzing the power domains the found power port names belonging to, unifying all the power source names in the same power domain, modifying the netlists of the black box IPs in the layout netlist, enabling ports with the same name to be virtually connected, comparing the layout and schematic uniformity, and enabling results to be uniform. By means of the comparative method of the layout and schematic uniformity of the multi-power-domain system with the black box IPs, detection efficiency is improved, detection risks can be reduced, and design cost is lowered.

Description

technical field [0001] The present invention relates to the field of semiconductor integrated circuits, in particular to a black box IP multi-power domain system layout and principle Figure 1 consistent method of comparison. Background technique [0002] In the existing chip design, the layout and principle must be carried out after the chip layout design is completed. Figure 1 Consistency comparison (Layoutversus Schematic, LVS) to ensure the consistency of layout and circuit schematic. as follows figure 1 As shown, it is the flow chart of the existing LVS. The existing LVS steps include the steps of extracting the layout netlist (Layout Netlist) from the layout database (Layout Database), and performing the comparison in the environment of the LVS design rule comparison run file (Runset) A step of comparing the layout netlist with the schematic netlist (Schematic Netlist) for consistency. [0003] In existing chip designs, in order to reduce chip power consumption, a ...

AI Technical Summary

Problems solved by technology

For designers, LVS can treat these modules only as black boxes, regardless of the internal circuit structure of the modules, and only consider the port connection relationship; but LVS will have a problem when dealing with the same-named ports in these black-box IPs: because there is no internal Circuits, these ports with the same name will be considered disconnected and unconnected on the layout (actually, the ports with the same name will be connected together in a complete module)

[0007] For the design of multi-power domain system with black box IP, the existing LVS technology is relatively inefficient in terms of efficiency, and there are also certain design risks

Images