Video multi-image synthesizing method, device and system

Abstract

The invention discloses a video multi-image synthesizing method, device and system. The method comprises that: a video processing field programmable gate array (FPGA) receives multipath videos and respectively corresponding addresses sent by a decoding module via a high-speed serial bus, and the address of each path of video is confirmed by the decoding module according to the requirement of multi-image layout; the received multipath videos are scaled, and size of each path of video after scaling is the same with that of a corresponding sub-image in multiple images respectively; each path of video after scaling is cached, and the corresponding address of each path of video after caching is corrected; and each path of video after scaling is respectively stored in corresponding memory space according to the corrected address. System resource can be saved, data transmission speed can be enhanced and image quality can be enhanced by the method.

Description

technical field [0001] The present invention relates to video conferencing technology, in particular to a method, device and system for synthesizing multiple video images. Background technique [0002] High-definition video conferencing terminals usually use such as figure 1 As shown in the hardware architecture, the working principle of the high-definition videoconferencing terminal is: the network communication module 110 receives the network packet sent by the remote videoconferencing terminal, sends it to the main control processor 109 for unpacking, and obtains the remote compressed video stream , then pass the compressed video data to the decoding module 105 through the system bus 108 between the decoding module, after the decoding module decompresses the video data, obtain the data in the original RAW format, then pass through the video interface (Video Port, VP) of the decoding module 106 is packaged into standard BT.1120 format video data, and sent to the video pro...

AI Technical Summary

Problems solved by technology

With the high-definition video conferencing terminal able to realize the function of the built-in Multipoint Control Unit (MCU), the data that needs to be transmitted between the encoding and decoding modules and the video processing FPGA has increased significantly, and the parallel VP interface can no longer meet the requirements of data transmission. need

When multiple channels of decoded video with high resolution and high frame rate need to be transmitted, the decoding module needs to scale the multiple channels of video to reduce the bandwidth of the data stream, and then transmit it to the video processing FPGA through the VP interface, and the video processing FPGA needs to process the video Secondary scaling and image extraction, followed by multi-image synthesis, increases system complexity, not only wastes system resources, but also reduces image quality

In addition, the parallel VP interface will occupy a lot of printed circuit board (PCB) wiring space; when the video clock frequency is high, especially when the video is in 1080P60 format, the bus timing is difficult to control

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