Semiconductor device manufacturing method

Abstract

The invention provides a method for manufacturing a semiconductor device. The method comprises forming a tensile stress layer subjected to nitrogen plasma processing in an NMOS area. Since the corrosion rate of a tensile stress silicon nitride subjected to the nitrogen plasma processing in a DHF is decreased compared to the corrosion rate of an unprocessed tensile stress silicon nitride, in a later virtual grid removal technology, only a small part of the tensile stress silicon nitride in the NMOS area is corroded and removed and a large part is reserved, so that enough stress can be provided to a channel, and adverse influences which may be exerted on a device structure in a subsequent step are avoided, thus the completeness of the device structure is ensured, and the technology integration of a rear grid technology and double strain stress layers can be realized.

Description

technical field [0001] The invention relates to the field of manufacturing methods of semiconductor devices, in particular to an integration method of a double strain stress layer applied in a CMOS gate-last process. Background technique [0002] After semiconductor integrated circuit technology enters the technology node of 90nm feature size, it becomes more and more challenging to maintain or improve transistor performance. After the 90nm node, stress technology is gradually adopted to improve device performance. At the same time, in terms of manufacturing process, the high-K metal gate technology in the gate last process (gate last) is also gradually adopted to meet the challenges brought about by the continuous reduction of devices. In the stress technology, the dual stress layer (DSL, dual stressliner) technology has high compatibility with conventional processes and low cost, so it is adopted by major semiconductor manufacturers. [0003] DSL technology refers to the...

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Problems solved by technology

Thus, DSL integration fails due to stress layer loss

In addition, for the case where TEOS is deposited on the device, although the TEOS covering the stress layer after CMP will protect the stress layer from corrosion, the corrosion rate of TEOS in DHF is also relatively high, and the process of removing the dummy gate insulating layer During the process, TEOS is in danger of being completely corroded by DHF, which will expose the underlying tensile stress silicon nitride to the environment of DHF, resulting in the corrosion of tensile stress silicon nitride

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