Data synchronization method

Abstract

The embodiment of the invention provides a data synchronization method and device. The method includes the first step of carrying out one-to-N demultiplexing on input data through set asynchronous clocks to obtain N paths of data and first synchronizing signals, wherein the transmission rate of each path of data is one-Nth of the transmission rate of the input data, and the cycle of the first synchronizing signals is the cycle of 2N asynchronous clocks, the second step of carrying out delaying on the first synchronizing signals through set synchronous clocks to obtain second synchronizing signals and third synchronizing signals, the third step of judging whether the second synchronizing signals are equal to the third synchronizing signals at each sampling edge of the synchronous clocks, generating edge trigger signals and carrying out counting operation, and the fourth step of carrying out sampling on the N paths of data sequentially according to the synchronous clocks and output counting values to obtain N-to-one multiplex output data. The method solves the problems that requirements for RAM resources are high and the delay time is long.

Description

technical field [0001] The invention relates to the field of digital signal transmission, in particular to a data synchronization method and device. Background technique [0002] As digital systems grow larger and more complex, two or more clock domains are increasingly used in logic designs. In different clock domains, it is inevitable that data will be transferred to each other. Since there will be a certain phase difference and short-term frequency jitter between two different clocks, in order to ensure reliable data transmission, the impact of timing on functions must be fully considered when designing, otherwise it will be divided into two clock domains Data synchronization between failed. [0003] At present, the data conversion from the asynchronous clock domain to the synchronous clock domain is usually implemented by the method of caching data in the dual-port RAM: the asynchronous clock is used as the write clock of the dual-port RAM, and the write clock generate...

AI Technical Summary

Problems solved by technology

[0005] The embodiment of the present invention provides a method and device for data synchronization to solve the problem of high requirements on the depth of RAM and long delay time in the existing data synchronization technology

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