Non-volatile semiconductor memory device

Abstract

Proposed is a non-volatile semiconductor memory device in which it is possible to more freely set the voltage used when accumulating charge in a selected memory cell transistor than a conventional one. In the non-volatile semiconductor memory device (1), when accumulating charge in a selected memory cell transistor (115), a high write inhibit voltage is applied through a P-type MOS transistor (9b) and a low write voltage is applied through an N-type MOS transistor (15a). A function for applying a voltage to the selected memory cell transistor (115) or a non-selected memory cell transistor (116) is thereby shared by the separate P-type MOS transistor (9b) and N-type MOS transistor (15a). This makes it possible to separately adjust, for example, the gate and source voltages of each of the P-type and N-type MOS transistors (9b, 15a) and finally to set the gate-substrate voltage to, for example, 4 V or other values.

Description

technical field [0001] The present invention relates to a nonvolatile semiconductor storage device. Background technique [0002] At present, a typical nonvolatile semiconductor memory device, such as a type of nonvolatile semiconductor memory device, has been well known, and this type of semiconductor memory device, for example, through the quantum tunneling effect, to the charge accumulation layer of the memory cell transistor Charges are internally accumulated so that a data writing process is performed (for example, refer to Patent Document 1). Actually, as shown in FIG. 6, this type of nonvolatile semiconductor memory device 100 has a structure in which high-order bit lines 101a, 101b and word lines 102a to 102h are arranged in a cross manner, and a plurality of memory cell transistors 103 They are arranged in rows and columns of a matrix with respect to the higher order bit lines 101a, 101b and word lines 102a to 102h. [0003] A plurality of first semiconductor swit...

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Problems solved by technology

[0023] However, the nonvolatile semiconductor memory device 100 having such a structure has the following defect: when the write prevention voltage from the unselected bit line 123 is applied to the unselected memory cell transistor 116 on the selected word line 120, due to the second One semiconductor switch 104b is constituted by an N-type MOS transistor. In order to turn on the first semiconductor switch 104b, it is necessary to apply a writing prevention voltage higher than 8[V], about 10[V], from the unselected bit line 123. V] gate voltage, then the problem of excessive voltage inevitably occurs

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