Method and system for replacing through holes in memory cell array layout data

Abstract

The invention discloses a method for replacing through holes in memory cell array layout data. The method comprises the steps of building a data sequence, sequentially building a memory cell chain table by the memory cells in the memory cell array layout data needed to be processed; recording the coordinates of the four angles of one second through holes of the memory cells; searching according to the sequence of the chain table; adding the coordinates of the four angles of the one second through holes of the existing memory cells unsuccessfully matched up with the existing one second through holes in the same data sequence into a data sequence; clearing away the coordinates of the four angles of the one second through holes successfully matched up with the one second through holes of the existing memory cells from the data sequence; and combining every two successfully matched one second through holes to be a to-be-replaced complete through hole. The invention further discloses a device for replacing the through holes in the memory cell array layout data. According to the method and the device, no matter what the two one second through holes of a complete through hole between every two adjacent memory cells of the memory cell array are in the same stratum of the layout, the through holes can be fully, accurately and quickly positioned and replaced.

Description

technical field [0001] The invention relates to a technology for processing semiconductor physical layout data, in particular to a method and system for replacing through holes in memory cell array layout data. Background technique [0002] The memory cell array layout data, based on different semiconductor process requirements, often needs to change the unit size of the through hole. The unit size of the hole is 0.28mμm*0.28μm. At this time, it is necessary to change the unit size of the through hole in the layout data of the memory cell array to 0.28mμm*0.28μm, such as figure 1 shown. Each memory cell of the memory cell array is distributed in multiple layout levels, and the entire through hole between two adjacent memory cells of the memory cell array is spliced ​​by two 1 / 2 through holes, and each 1 / 2 through hole Positioned by the coordinates of its four corners, the coordinates of two corners are the same between the two 1 / 2 through holes forming the overall through ...

AI Technical Summary

Problems solved by technology

When two adjacent memory cells are at the same layout level, the through holes between the two adjacent memory cells can be located by the conventional search method, and the through holes can be completely and accurately replaced; but when the two adjacent memory cells are not in the same At the layout level, since half of the entire via hole is located in one layout level and the other half of the entire via hole is located in another layout level, the positioning of the via hole between two memory cells is more difficult.

The existing practice is to use a layout tool such as Virtuoso to visually search for the entire via hole between two adjacent memory cells that are not in the same layout level, and then replace the via hole. The number of through holes between storage units is extremely large (up to more than 30,000), which takes a lot of time and also poses a huge risk. In case of individual through hole data replacement errors, the through holes will be lost. Major problems such as circuit failure

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