Low voltage difference signal LVDS composition circuit

Abstract

The invention provides a low voltage difference signal LVDS composition circuit comprising the following modules: an LVDS module; a first current mirror module and a second current mirror module; a sampling module used for sampling common mode level outputted by the LVDS module; a feedback control network module used for respectively generating a first feedback signal and a second feedback signal according to the sampled common mode level, respectively sending the first and second feedback signals to the first current mirror module and the second current mirror module, and adjusting output current of the first and second current mirror modules; when the common mode level is higher than a first preset value, the output current of the first current mirror module is reduced and the output current of the second current mirror module are increased; when the common mode level is smaller than a second preset value, the output current of the first current mirror module is increased and the output current of the second current mirror module is reduced; the first preset value is bigger than the second preset value; the LVDS composition circuit can satisfy normal work under high speed state, and adaptation capability of PVT in a large scope.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a low-voltage differential signal LVDS structure circuit. Background technique [0002] The rapid development of CMOS (Complementary Metal Oxide Semiconductor, Complementary Metal Oxide Semiconductor) integrated circuits makes the transmission data continuously increase and the transmission speed continuously increase. In the past, high-speed data was usually transmitted with a parallel port, but this consumed more area and power consumption. The proposal of the LVDS (Low Voltage Differential Signal) standard provides a fast and low-consumption data transmission method. The field of LVDS design involves the application of low-voltage differential output in high-speed fields. [0003] in, figure 1 It is a schematic diagram of the basic structure of LVDS. In the figure, switches 101, 104 and 102, 103 are turned on alternately, and outp and outn alternately output low ...

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Problems solved by technology

[0005] The disadvantage of the prior art is that, on the one hand, due to the fast working speed, the general common-mode feedback sometimes cannot reach the required speed, causing the common-mode level of the LVDS output to deviate from the corresponding required range, and the data cannot be transmitted correctly

On the other hand, due to the small output voltage difference of LVDS, for example, it is 200 millivolts in the MIPI (Mobile Industry Processor Interface) protocol, and the typical value is 300 millivolts for high level and 100 millivolts for low level. Volts), under such low dropout conditions, LVDS often cannot adapt to changes in process PVT (Process, Voltage, Temperature), resulting in errors in output data

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