Replacement processing method and device for cache blocks in caches

Abstract

An embodiment of the invention provides a replacement processing method and device for cache blocks in caches. A zone bit is added into each cache line in each cache except for an L1 cache to indicate whether data in the cache line exist in a previous cache, the situation that cache lines contained in the previous cache are replaced in the current cache is decreased as far as possible, and further expenditure caused by the fact that the cache lines in the previous cache are replaced is reduced; hit rate of the caches can be increased, and cache access delay can be reduced.

Description

technical field [0001] The embodiments of the present invention relate to data storage technologies, and in particular to a method and device for replacing and processing cache blocks in a cache memory. Background technique [0002] Cache memory (cache) was first proposed by Wilkes in 1951 to make up for the speed difference between the processor and the memory, and is the most important part of the storage system. In the prior art, the cache generally adopts a hierarchical structure, figure 1 It is a schematic diagram of the cache hierarchy structure in the prior art, such as figure 1 The three-level cache structure of L1 cache, L2 cache and L3 cache is adopted, and the access speed decreases successively, and the capacity increases successively. The L1 cache is the superior cache for the L2 cache, and the L2 cache is the superior cache for the L3 cache. If all the data in the upper-level cache exists in the current-level cache, then the organization of this cache is inc...

AI Technical Summary

Problems solved by technology

[0004] In the cache organized in an inclusive manner, since the caches at all levels only make statistics based on the access status of the cache at this level, the usage of the low-level caches may not be true, which in turn leads to inefficient replacement strategies and affects memory access performance.

For example, when the L2 cache performs cache line replacement, it may replace a cache line that is frequently hit in the L1 cache; due to the inclusive organization method, the corresponding cache line in the L1 cache will also be replaced, which will affect memory access. performance

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