Grid side wall thinning process

Abstract

The invention provides a grid side wall thinning process. The grid side wall thinning process comprises the steps that first, after a grid and a grid side wall are formed on a semiconductor substrate, the entire semiconductor substrate is coated with an anti-reflection layer; then, a photoetching process and an etching process are used for patterning the anti-reflection layer; the anti-reflection layer is used as a mask, a dry etching process is used for etching the side wall downwards, and therefore thinning of the side wall in the width direction is achieved. The anti-reflection layer covers the top of the grid and the top of the side wall, in the thinning process, the top of the grid and the top of the side wall can be prevented from being damaged so that a process window can be expanded, the width of thinning is increased, and the thinning effect of the side wall is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a gate side wall thinning process. Background technique [0002] With the continuous shrinking of the process size, especially 65nm and below, in order to enhance the performance of the device, the stress proximity technique (Stress Proximity Technique, SPT) is usually used to thin the width of the sidewalls on both sides of the gate, so that the subsequent The film layer is deposited closer to the channel (channel) to enhance device drive current. [0003] Usually, the process of using the SPT process to thin the gate sidewall includes: directly performing one-step dry etching after the formation of the sidewall and silicide, so as to reduce the width of the sidewall. [0004] Using the above method, in dry etching, while thinning the sidewall horizontally, it is also inevitable to etch to the top of the sidewall, please refer to figure 1 , figure 1 It is a schematic d...

AI Technical Summary

Problems solved by technology

Damage to the top of the gate spacer can cause device leakage and ultimately degrade device performance

In the actual process, in order to reduce the damage on the top of the gate sidewall, the amount of etching in the horizontal direction has to be limited. In this way, the etching in the horizontal direction of the sidewall is limited by the vertical direction, and the process window is very small, which affects the gate. Effect of side wall thinning

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