Unlock instant, AI-driven research and patent intelligence for your innovation.

Latch capable of resisting dual-node upset

A dual-node flip and latch technology, applied in electrical components, logic circuits, pulse technology, etc., can solve the problems of inability to resist single event pulses and few reports

Inactive Publication Date: 2014-07-30
TIANJIN UNIV
View PDF1 Cites 7 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, there are few reports about
Existing latches that are resistant to MBUs have some problems. For example, the proposed structure may be proposed under the assumption that a single radiation particle will not cause simultaneous flipping of sensitive nodes in different wells, or it may not be resistant to noise on the input signal. Single event Transient (SET)

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Latch capable of resisting dual-node upset
  • Latch capable of resisting dual-node upset
  • Latch capable of resisting dual-node upset

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0013] Guard-Gate (C unit) (eg figure 1 (a) shows its transistor-level structure, (b) its logic symbol, and (c) its truth table). The structure is composed of P-type transistors PG0, PG1 and N-type transistors NG0, NG1. The source of PG0 is connected to VDD, the drain is connected to the source of PG1; the drain of PG1 is connected to the drain of NG0, the source of NG0 is connected to the drain of NG1, and the source of NG1 is connected to GND. The input signal A is connected to the gate terminals of PG0 and NG0, and the input signal B is connected to the gate terminals of PG1 and NG1. The connection point between the drain terminal of PG1 and the drain terminal of NG0 is used as the output signal Out. Among them, the Guard-Gate outputs a high-impedance state when the two inputs are not the same. When the two input signals are the same, the function of the unit is identical to that of an inverter. delay unit (such as figure 2 shown) is composed of two inverters (INV0 an...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to the field of radiation hardened integrated circuit designing, and provides a latch capable of resisting dual-node upset and resisting SET on an input line and SET on a clock line. By the adoption of the technical scheme, the latch capable of resisting the dual-node upset is composed of three Guard-Gate units, three delay units and two transmission gates. An input signal of the latch arrives at a first node 1 via the first transmission gate T1 and then is divided into two branches, one branch passes through the first delay unit D1, and the other branch serves as one input signal of the second Guard-Gate unit. The output of the first delay unit D1 serves as the other output signal of the second Guard-Gate unit, one input of the first Guard-Gate unit and the input of the second delay unit D2 at the same time. The output of the third Guard-Gate unit forms a feedback circuit. The latch is mainly applied to radiation hardened integrated circuit designing.

Description

technical field [0001] The invention is in the field of anti-radiation integrated circuit design, in particular, it designs and adopts time-domain redundancy and space redundancy technologies to reinforce sequential circuits. So that the sequential circuit has the ability to resist single event upset (Single event upset, SEU) and multi-bit upset (Multiple-bit upsets, MBUs). In particular, it relates to latches that are resistant to double-node flipping. technical background [0002] For digital circuits used in space environments, especially sequential circuits, the occurrence of single event upset (Single event upset, SEU) will seriously affect the correctness of chip functions. As the size of integrated circuits decreases and the supply voltage of chips decreases, the probability of multiple-bit upsets (MBUs) is gradually increasing, thereby affecting the performance of the circuit. [0003] For SEU protection, circuit design can be used to reinforce the circuit. The re...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H03K19/094
Inventor 徐江涛李新伟姚素英史再峰高静高志远聂凯明
Owner TIANJIN UNIV