Measuring method for capacity parameters of each chip on silicon chip

Abstract

The invention provides a measuring method for capacity parameters of each chip on a silicon chip, comprising the steps of selecting a tested silicon chip, transferring a measuring probe of a capacitance meter to be above each chip on the tested silicon chip to carry out a new round of non-contact idle measurement, so as to obtain zero capacitance data of each chip in different positions on the tested silicon chip under current measurement environment; providing a to-be-tested silicon chip, enabling the measuring probe to respectively contact with each chip on the to-be-tested silicon chip to carry out formal measurement, wherein after each chip is measured, subtracting the measurement value by the zero capacitance data of the chip in the same position on the tested silicon chip, so as to obtain the actual capacitance of each tested chip on the to-be-tested silicon chip; comparing the actual capacitance of each tested chip after calculation zero setting with a code value respectively, judging whether the chip is qualified or not, and recording and storing as data. According to the invention, distribution effect and parasitic effect of capacitance of the back and the surface of the silicon chip can be overcome, quick and accurate measurement can be carried out on small capacitance parameters of each chip on the silicon chip, and the requirement of mass production can be met.

Description

technical field [0001] The invention relates to the technical field of integrated circuit testing, in particular, the invention relates to a method for measuring capacitance parameters of each chip on a silicon wafer. Background technique [0002] In the chip (die) capacitance parameter test in the silicon wafer (wafer) production of integrated circuits, generally a measurement probe touches the electrode of the measured capacitor on the front of the chip, and the other electrode of the measured capacitor is sucked from the back of the silicon chip. Conductive suction cup leads. That is to say, the backside of the entire silicon wafer is the common electrode of all chips. [0003] Due to the distribution effect and parasitic effect of the surface capacitance on the back of the silicon wafer, the parasitic capacitance between the electrodes on the back of the silicon wafer and the chips at different positions on the front of the silicon wafer is different. Taking a silicon ...

AI Technical Summary

Problems solved by technology

However, one zero adjustment takes about 1 second

If each chip is zeroed and then tested, it is unacceptable for mass production, and only a small number of chips on the silicon wafer can be sampled and tested

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