Chip packaging structure

Abstract

Disclosed is a chip packaging structure which includes a lead frame, a chip, at least one bus and a lead group. The lead frame includes a chip seat, a plurality of signal pins and a plurality of grounding pins. The signal pins and the grounding pins are arranged around the chip seat. The chip is arranged on the chip seat of the lead frame. The chip is provided with a plurality of grounding bonding pads. The buses are connected with part of the grounding pins of the lead frame. The lead group is connected with the grounding bonding pads of the chip, the signal pins, the grounding pins and the buses.

Description

technical field [0001] The present invention relates to a packaging structure, and in particular to a chip packaging structure. Background technique [0002] The purpose of chip packaging is to provide proper signal path, heat dissipation path and structural protection of the chip. Traditional wire bonding technology usually uses a leadframe as a chip carrier. [0003] Generally speaking, during the wire bonding process, most of the wires are bonded from the signal pins of the lead frame to the I / O pads of the chip. However, when the chip requires more functions, that is, when there are more signal pads with different functions on the chip, the required number of signal pins of the lead frame is relatively increased. Therefore, not only the number of signal pins on the lead frame is likely to be insufficient, but also the signal pads of the chip need to be set in one-to-one correspondence with the signal pins, which limits the position and relationship of non-signal pads. ...

AI Technical Summary

Problems solved by technology

[0004] The present invention provides a chip packaging structure to solve the problem of insufficient number of groups of non-signal pads and non-signal pins and the problem of excessive distance between signal pins and non-signal pins

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